Issue with Secure Booting from Bank 4 - LS1043A

[ejaz]

On NXP reference board based on LS1043A SOC we are not able to secure boot using Bank 4 (selected via CPLD). It fails and shows that it is in non secure mode (when reading status registers). But the same procedure works fine and we are able to successful secure boot from Bank 0.

We do have a system requirement to be able to sometimes boot from the alternate Bank 4.

Is this a limitation of the CPLD/reference board or LS1043A SOC? Or is there something that may not be documented in the NXP documentation?

Please advise.

[yipingwang]

Hello Ejaz Ahmed,

There is no limitation for secure boot from bank4 on LS1043 SoC.

Please refer to the section "3. Deploy Secure Boot Images to the Target and Write SRKH Mirror Register" in this document Setting up Secure Boot on PBL Based Platforms in Prototype Stage.

This section introduces how to do secure boot validation in the prototype stage. First blow OTPMK keys to fuse array from CCS, then setup u-boot in Bank0, deploy secure boot images to Bank4, swith to Bank4(with cpld), use CCS to connect to the target board to write SRKH.

Have a great day,
Yiping

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