Interrupt priority bitmask for LS1043A GIC Distributor

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Interrupt priority bitmask for LS1043A GIC Distributor

Contributor II


Quick question for the LS1043A expert regarding the GIC setting for interrupt priority in Linux.

Currently the default value of 0xA0 is written into GIC distributor for all interrupts, it is said from Arm that the number of priority level are either 256,128,... it is up to the chip vendor to decide how many level they implement for their respective design.

I scan thru all the NXP doc but cannot find the info.

I know the lower value the higher the priority, can some one know the actual number of interrupt priority level for the LS1043A or better the bit mask if there are another level of priority.

Also, anybody know why 0xA0 was the default value?

Thank you in advance.


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NXP Employee
NXP Employee

There is no information about the reason for setting this interrupt priority as default.

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