Interrupt low time for ARMv8-A53

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Interrupt low time for ARMv8-A53

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pro-supportengi
NXP Employee
NXP Employee

I want to now what is the minimum low time required for the ARMv8-A53 interrupt to detect as a valid interrupt.

Pls guide with proper reference.

For example, the ethernet driver for the LS1043ARDB and/or toggling a GPIO for an interrupt?

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r8070z
NXP Employee
NXP Employee

Have a great day,

The LS1043A interrupt controller (GIC) inputs are asynchronous to any visible clock. GIC inputs are required to be valid for at least 3 SYSCLKs to ensure proper operation.

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pro-supportengi
NXP Employee
NXP Employee

What is the best and worst case latency for interrupts on the LS1043A?  Latency between the occurrences of the interrupt and the start of the ISR.

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