IFC interface

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IFC interface

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Roei89
Contributor I

Our IFC interface implementation for CPU and NAND flash will include connection to FPGA on the same lines for IFC.

 

And Chip selects (CSn)  will be routed to FPGA and NAND flash,  for control.

 

This connection concept is implemented in NXP EVB schematic.

 

Please confirm that this interface is validate.   

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