IFC clock computation LS2044

[benoitmasse]

Hi,

I want to determine at which speed (min to max) the IFC can run with the following clock configuration:

1- SYSCLK 133 MHz  (set to single end by cfg_eng_use0 to H)

2- RCW 6-2 set to 0b10000 - 16:1 ( set System PLL to generate 2133 MHz)

3- Platform clock is derived from System PLL / 2 which is 1066 MHz (Figure 4-2 p. 299) see Ref below.

4- Platform clock is again divide by 2 before feeding IFC module (533 MHz)

5- With IFC control Register CCR, we can select bypass, divide by 2, 4 or 8.

6- My IFC Bus speed can run at 533 MHz, 267 MHz, 133 MHz or 67 MHz.

Am I right or I missed something?

My reference is QorIQ LS2088A Reference Manual, Rev. 1, 09/20

Thanks, 

[benoitmasse]

Hi,

After reading many time the Ref Manual and the Data book my conclusion is: if I want to run IFC Bus at 50 MHz I have to configure Registers as:

SYSCLK = 133.33 MHz ---> System PLL (SYS_PLL_RAT 12:1) = 1600 MHz ---> Platform clock (1600 GHz / 2) = 800 MHz ---> 400 MHz / 2 = 200 MHz ---> IFC CCR ( / 4 )  = 50 MHz

By the way what is the Coherency Domain frequency ? (the 1600 MHz ?)

For Core Frequency:

SYSCLK = 133.33 MHz ---> CGA_PLL1 (15:1) = 2000 MHz ---> CGA_PLL1(bypass) = 2000 MHz = Core Frequency

With this configuration, I respect secion 4.1 (Data Sheet).

Did I do it right ?

Thank for you time,

[Bulat]

The processor has some clock limits that should not be exceeded. For example, maximum platform clock frequency is 800MHz (depends on the part number), maximum IFC clock freqeuncy is 100MHz. In other words, SYSCLK frequency, SYSCLK ratio and CCR divider must be chosen such that the resulting platform and IFC clock frequency do not exceed their respective maximum (or minimum) operating frequencies. Details can be found in section 4.1 of the LS2084A/LS2044A Data Sheet.

Regards,

Bulat