How to resolve the LS2085A QDS boot error

[anandhakumarm]

Hi All,

I'm using LS2085A QDS board and im facing errors like the following. The boot log is as followa

U-Boot 2015.07-rc1Layerscape2-SDK+g7e8bad0 (Oct 08 2015 - 20:08:11)                   

SoC:  LS2085E (0x87010010)                                                 

Clock Configuration:                  

       CPU0(A57):1600 MHz  CPU1(A57):1600 MHz  CPU2(A57):1600 MHz

       CPU3(A57):1600 MHz  CPU4(A57):1600 MHz  CPU5(A57):1600 MHz

       CPU6(A57):1600 MHz  CPU7(A57):1600 MHz

       Bus:      600  MHz  DDR:      1333.333 MT/s     DP-DDR:   1333.333 MT/s

Reset Configuration Word (RCW):       

       00: 40282830 40400040 00000000 00000000

       10: 00000000 00200000 00200000 00000000

       20: 01812980 00002580 00000000 00000000

       30: 00000e0b 00000000 00000000 00000000

       40: 00000000 00000000 00000000 00000000

       50: 00000000 00000000 00000000 00000000

       60: 00000000 00000000 00027000 00000000

       70: 3f350000 00000000 00000000 00000000

Model: Freescale Layerscape 2085a QDS Board

Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 0

FPGA: v5 (LS2085AQDS_2015_0218_1606), build 132 on Wed Feb 18 22:06:38 2015

SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 100 separate SSCGMHz

SERDES2 Reference : Clock1 = 100 separate SSCGMHz Clock2 = 100 separate SSCGMHz

I2C:   ready

DRAM:  Initializing DDR....using SPD

Detected UDIMM 18ASF1G72AZ-2G1A1

Detected UDIMM 18ASF1G72AZ-2G1A1

Controler 0 timeout, debug_2 = 2100

Controler 0 timeout, debug_2 = 2500

Waiting for D_INIT timeout. Memory may not work.

Controler 1 timeout, debug_2 = 100

Controler 1 timeout, debug_2 = 1500

Waiting for D_INIT timeout. Memory may not work.

DP-DDR:  Detected UDIMM 18ASF1G72AZ-2G1A1

The errors are indicated in red color, please help me to fix this issue.

Note: I didnt change any DDR related files, all the default images are already loaded in the board..

[yipingwang]

Hello Anandha Kumar,

It seems that you customized the RCW file based on the default one, Can you boot up the board successfully with the default RCW file? If the problem also exists, would you please provide the switch configuration on your target board?

Have a great day,
Yiping

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[anandhakumarm]

Hi Yiping,

I'm using the default RCW file only, also all the switch settings are proper and verified as per the user guide from Freescale document. I guess this might be due to frequency mismatch and some DDR issue with the board. Please comment on the same. Thanks for your valuable reply.

[yipingwang]

Hello Anandha Kumar,

It looks that you used the u-boot image built from 20150828, but RCW is not from this release.

I built RCW and u-boot for LS2085AQDS with Layerscape2-SDK-20150828, please refer to the attachment.

Please try whether these images could work on your target board.

You could program these images to NOR flash from other bank if possible, or use CodeWarrior to do flash programming.

Have a great day,
Yiping

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[anandhakumarm]

Hi Yiping,

I flashed above images using Codewarrior flash programmer. Since the problem remains same.

Boot log:

===========

U-Boot 2015.07-rc1Layerscape2-SDK+g7e8bad0 (Jan 05 2016 - 15:43:31)

SoC:  LS2085E (0x87010010)

Clock Configuration:

       CPU0(A57):1600 MHz  CPU1(A57):1600 MHz  CPU2(A57):1600 MHz 

       CPU3(A57):1600 MHz  CPU4(A57):1600 MHz  CPU5(A57):1600 MHz 

       CPU6(A57):1600 MHz  CPU7(A57):1600 MHz 

       Bus:      600  MHz  DDR:      1333.333 MT/s     DP-DDR:   1333.333 MT/s

Reset Configuration Word (RCW):

       00: 40282830 40400040 00000000 00000000

       10: 00000000 00200000 00200000 00000000

       20: 00c12980 00002580 00000000 00000000

       30: 00000e0b 00000000 00000000 00000000

       40: 00000000 00000000 00000000 00000000

       50: 00000000 00000000 00000000 00000000

       60: 00000000 00000000 00027000 00000000

       70: 492a0000 00000000 00000000 00000000

Model: Freescale Layerscape 2085a QDS Board

Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4

FPGA: v5 (LS2085AQDS_2015_0218_1606), build 132 on Wed Feb 18 22:06:38 2015

SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 100MHz

SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz

I2C:   ready

DRAM:  Initializing DDR....using SPD

Detected UDIMM 18ASF1G72AZ-2G1A1

Detected UDIMM 18ASF1G72AZ-2G1A1

Controler 0 timeout, debug_2 = 2100

Controler 0 timeout, debug_2 = 2500

Waiting for D_INIT timeout. Memory may not work.

Controler 1 timeout, debug_2 = 2100

Controler 1 timeout, debug_2 = 2500

Waiting for D_INIT timeout. Memory may not work.

DP-DDR:  Detected UDIMM 18ASF1G72AZ-2G1A1

=============

May i know why this issue is occurred and how to solve it?

Thanks for your great responses,

Thanks Regards,

-Anandha Kumar

[naveennvn]

Hi all,

Can anyone help me on, to fix this issue?

Thanks,

-Naveen

[yipingwang]

Hello Naveen,

It seems that you have used this LS2085AQDS board for several months, why did you encounter this problem suddenly? I am not sure what modification  you have done, I suspect you updated to the new version u-boot recently, and this u-boot is not compatible with the FPGA firmware on your target, We use FPGA v7 on the board farm board.

So I suggest you program old version u-boot back and check whether this problem remains, if it disappears, you could consider about updating to new version FPGA.

Have a great day,
Yiping

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[naveennvn]

Hi Yiping,

From Starting itself we are using EAR4 images. Recently we changed to EAR5 images, for that also its working fine for a while.

Now we are facing this boot error issue. I flashed default EAR4 images via JTAG programmer.

But still the problem remains same.

What's the solution for that?

Thanks,

-Naveen

[yipingwang]

Hello Naveen,

Please use CodeWarrior to debug a sample program in DDR memory to check whether the program could be executed successfully in DDR.

Thanks,

Yiping

[naveennvn]

Hi Yiping,

i flashed the new uboot image with debug enabled and dumped the DDR registers.

DDR dump is working fine. Please find the attachment.

Thanks,

-Naveen

[ed_swarthout]

Is the processor on this board in a socket?  If so, can you re-seat the processor to see if this is a mechanical issue?

[naveennvn]

Hi,

For me still the issue remains same.

Is there any other way to fix this issue?

Thanks,

-Naveen