Hi NXP experts,
I am trying to optimize the ATF boot time, and it shows the DDRC initialize will cost too much time; The code annotation of ddrc_set_regs shows that:
/*
* If supported by the platform, writing to DDR controller takes two
* passes to deassert DDR reset to comply with JEDEC specs for RDIMMs.
*/
int ddrc_set_regs(const unsigned long clk,
const struct ddr_cfg_regs *regs,
const struct ccsr_ddr *ddr,
int twopass)
{
... ...
if (twopass == 2)
goto after_reset;
... ...
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock
* control register is set. Because all DDR components are connected to
* one reset signal, this needs to be done in two steps. Step 1 is to
* get the clocks started. Step 2 resumes after reset signal is
* deasserted.
*/
if (twopass == 1) {
udelay(200);
return 0;
}
after_reset:
... ...
}
static int write_ddrc_regs(struct ddr_info *priv)
{
int i;
int ret;
for (i = 0; i < priv->num_ctlrs; i++) {
ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0);
if (ret) {
ERROR("Writing DDR register(s) failed\n");
return ret;
}
}
return 0;
}
My board is using UDIMM(no dimm) so it always use twopass=0 and the initialize will be like this:
START -> INIT DDRC1 -> WAIT DDRC1 -> INIT DDRC2 -> WAIT DDRC2 -> FINISH
So how to make the initialize sequence like below:
START -> INIT DDRC1 -> INIT DDRC2 -> WAIT DDRC1 -> WAIT DDRC2 -> FINISH
the twopass=1/2 is only for RDIMM, when force use twopass=1/2, it always get stuck.
Anyone can help let me know how to deal it?
