How to generate phase-aligned 1PPS from LS1028ARDB?

[mjstudio]

Hi,

I have an external Skyworks PLL clock which outputs 125MHz syc clock.

I have connected the 125MHz external sys clock to 1588_CLK_IN (J11 pin9) of NXP LS1028ARDB to trigger the 1588 timer counter (TMR_CNT). RCW field EC1_SAI4_5_PMUX is set to b101. I need to generate 1PPS from 1588_PLUSE_OUT2 and the 1PPS shall be need phase-aligned pulses.

Now I want to set the NXP LS1028A 1588 timer to normal mode as per the reference manual and Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors.

Suppose my desired nominal frequency is 100MHz as per the document above. I need to generate 1PPS from NXP LS1028ARDB  Below is the register I have set.

TMR_CTRL[TCLK_PERIOD] = 10ns

TMR_CTRL[CKSEL] = 00

MR_PRSC = 2

TMR_ADD=2^32*100/125 = 0xCCCCCCCD

TMR_CTRL[TE] =1

MR_CTRL[FS] =1

Since 1PPS is required and needs phase-aligned pulse, I try to set TMR_FIPER1 to 10^9 ÷ TCLK_PERIOD and it doesn’t work (1PPS is not phased aligned and the offset between this 1PPS and that from GM is 4us, furthermore, the phase offset becomes bigger and bigger as time passes). But as per the document, the TMR_FIPER1 shall be set to

(MR_PRSC × tclk_per × N) – tclk_per  

I don’t know how to set the N.

And the TMR_ALARM1 also need a value.

So could anybody let me know what values should be written to TMR_ALARM1 and TMR_FIPER1?

BTW, do I need to set any bits in TMR_TEMASK register? I see some of the event enable bits there (OFF by default) but I don’t know if I shall set them to ON.

Best Regards,

Jin Mai

[mjstudio]

Hi,

Thank you for your comments. My ext clock is 125MHz, and my nominal frequency is 100MHz. Is my configuration below correct?

TMR_CTRL[TCLK_PERIOD] = 10 ns

TMR_FIPER1 = 999,999,990       (10^9 - 10)

TMR_CTRL[CKSEL] = 00

MR_PRSC is the default value 0x00000002 after EVB is rebooted. I didn't change it.

For the TMR_ALARM1, I read the TMR_CNT and then add 3 seconds to it and then assign the sum to TMR_ALARM1.

cnt_l=`busybox devmem 0x1f812009c 32`
cnt_h=`busybox devmem 0x1f8120098 32`

((alarm1_h=cnt_h+3))

alarm1_h=`printf "0x%.8X\n" $alarm1_h`
echo $alarm1_h

#ALARM1 to trigger 1pps
busybox devmem 0x1f81200bc 32 0x3B9ACA00
busybox devmem 0x1f81200b8 32 $alarm1_h

[Chavira]

1. Program TMR_FIPER1 to a value that will generate a pulse every second.
2. To trigger FIPER1 by ALARM1, set TMR_CTRL[FS].
3. Program ALARM1 to a value which is a whole number of seconds, and greater than the present
TMR_CNT. In the formula below, n seconds are added to TMR_CNT. The sum is divided by 10e9 and the integer quotient results in a whole number of seconds.

For example, if TMR_CNT = 5.3 seconds and n = 2 seconds,
TMR_ALARM1 = floor(7.3*10e9, 10e9) = 7 seconds

4. Enable the timer
The hardware waits for TMR_ALARM1 to expire before enabling the count down of TMR_FIPER1. The end result is that TMR_FIPER1 pulses every second after the original timer ALARM1 expires.
If the PPS signals need to be phase-aligned to the prescale output clock, the alarm value should be programmed 1 clock period less than the desired value.
To track the prescale output clock, users must the FIPER by writing a new value to the register before enabling the FIPER. The FIPER value can be calculated as shown in the following equation:

Value of FIPER = (prescale_value × tclk_per × N) – tclk_per

For example, if prescale = 9 and clock period = 10, the FIPER can obtain the following values: 80, 170, 260.......

If an application chooses to change the value of TMR_CNT for
synchronization, the FIPER should be stopped. Value of ALARM1 should
be re-calculated to trigger FIPER1 again.

[Chavira]

Fiper = must be programmed to an integer multiple of
TMR_CTRL[TCLK_PERIOD] value to ensure a period pulse being generated correctly.

The output FIPER pulses are generated 1 timer reference clock after ALARM1 triggers.

TMR_ALARM1 = The corresponding alarm event in TMR_TEVENT is set when the current time counter becomes equal to or greater than the alarm time compare value in TMR_ALARM1_L/H.

The value programmed in this register must be an integer multiple of
TMR_CTRL[TCLK_PERIOD] in order to get correct result