GPIO on LS1021a-TWR

[bjashka]

We would like to use GPIO of LS1021a. We have Freescale board LS1021a-TWR.

We tried to operate few pins of GPIO3 port by modification of RCW in u-boot. In spite modification external signals are not affected by PDAT register value and not all the bits of PDAT can be set high.

Then, this is the question: What GPIOs we can use without affecting basic LS1021a-TWR functionality like Linux shell over UART, networking and PCIe.

[ufedor]

Hello,

The GPIO usage is described in the TWR-LS1021A Reference Manual, 2.21 GPIO pins.

Available GPIOs are GPIO3[13-14].

Which GPIO3_GPDIR value is used for the GPIO test?

[bjashka]

Yes, we tried to change state of GPIO3_13 and GPIO3_14.

In order to do so, we have modified EC1 field RCW to be 0b001 in yocto 1.8 rcw project and we have built sdboot image of u-boot.

Then, booting from SD, gives the following RCW snapshot in u-boot:

       00000000: 0608000a 00000000 00000000 00000000

       00000010: 20000000 00407900 60040a00 21046000

       00000020: 00000000 00000000 00000000 00038000

       00000030: 00080000 281b7340 00000000 00000000

highlighted nibble reflects our change.

Then, we tried to manage PDIR and PDAT register from u-boot by mw.l / md.l commands as follows:

=> mw.l 0x2320008 0x00000000 1

=> md.l 0x2320000

02320000: ffffffff 00000000 00000000 0000fe3f    ............?...

=> mw.l 0x2320008 0xffffffff 1

=> md.l 0x2320000

02320000: ffffffff 00000000 0000fe3f 0000fe3f    ........?...?...

Thus, some unpredicted results are observed:

1. we can't drive all the pins high in PDAT

2. the GPIO3_13 and GPIO3_14 pins signals are stay low for any value of PDAT register.

[ufedor]

Based on feedback from SW/design team If we want use all the GPIO3, we should set all the GPIO3 pin by RCW.

Include: EC1,EC2,EC3 and MDC_MDIO. You don't have option to only select subset of the GPIO3 pins. This is applicable to all GPIO ports.

416-418 EC1 = 001 GPIO3[2:14]

419-421 EC2 =001 GPIO3[15:27]

422-424 EC3 =001 GPIO3[28:31]

425-426 MDC_MDIO =01 GPIO3[0:1]

Unfortunately this information not explained in the RM.

And the reference rcw:

       00000000: 0608000a 00000000 00000000 00000000

       00000010: 20000000 00407900 60040a00 21046000

       00000020: 00000000 00000000 00000000 00038000

       00000030: 00080000 24bb7200 00000000 00000000

To check the pull high/low, you set the gpio direction to output. Here is our log:

=> mw.l 0x2320000 0xffffffff 1

=> md.l 0x2320000 4

02320000: ffffffff 00000000 ffffffff ffffffff    ................

=> mw.l 0x2320008  00000000 1

=> md.l 0x2320000 4

02320000: ffffffff 00000000 00000000 ffffffff    ................

[ufedor]

Please note that RCW[EC1] controls only GPIO3[2:14].

Also please note that GPIO registers are big-endian.

Bit[13] corresponds to 0x0004_0000.