Hi all,thanks for the above replies.They are really useful. I have few more doubts regarding X72 DDR4 configuration using 5 - 1G16 devices. Hope you people clarify.
1) How to input Vrefca 0.6v to DDR4. will it need a dedicated 0.6v power supply (as in Ls1046/43 RDB)? or can it be derived from GVDD(1.2V) through a potential divider(as in FRWYLS1046A-PA).
2) If CK_C, CK_T differential clock for DDR4 requires Termination(may be Z0), What will be the value of it?
3) Do we need to place SPD EEPROM As per JEDEC?
4) Certain Pins like BG1, CS1_n, CKE1, ODT1 are not used in X16 configuration. In that case, shall we keep them Open or any termination required?
5) Since we are not using the upper byte of ECC DDR4, We should terminate UDQS_t and UDQS_c of DDR4 IC. In micron guidelines UDQS_t is connected to VDD and UDQS_c is grounded. but this is contradicting with NXP's FRWYLS1046A-PA schematic. and suggest us any other guidelines WRT DDR4.
Thanks in Advance.