DDR4 interface to LS1046

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DDR4 interface to LS1046

1,470 Views
Urmila_123
Contributor II

Hi all,

we would like to interface DDR4 to LS1046  by using MT40A1G16KH-062E AAT:E component from micron. 4 such devices are directly connected to 64bit DDR4 controller of LS1046 and for ECC also, can we use the same device by connecting lower order data lines of DDR4 device to 8 ECC lines of LS1046 and making the remaining Data lines of device NC? will This processor accept such DDR4 topology? 

Thanks in Advance!

 

 

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5 Replies

1,409 Views
Urmila_123
Contributor II

Hi all,thanks for the above replies.They are really useful. I have few more doubts regarding X72 DDR4 configuration using 5 - 1G16 devices. Hope you people clarify.

1) How to input Vrefca 0.6v to DDR4. will it need a dedicated 0.6v power supply (as in Ls1046/43 RDB)? or can it be derived from GVDD(1.2V) through a potential divider(as in FRWYLS1046A-PA).

2) If CK_C, CK_T differential clock for DDR4 requires Termination(may be Z0), What will be the value of it?

3) Do we need to place SPD EEPROM As per JEDEC?

4) Certain Pins like BG1, CS1_n, CKE1, ODT1 are not used in X16 configuration. In that case, shall we keep them Open or any termination required? 

5) Since we are not using the upper byte of ECC DDR4, We should terminate UDQS_t and UDQS_c of DDR4 IC. In micron guidelines UDQS_t is connected to VDD and UDQS_c is grounded. but this is contradicting with NXP's FRWYLS1046A-PA schematic. and suggest us any other guidelines WRT DDR4.

Thanks in Advance.

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1,400 Views
ufedor
NXP Employee
NXP Employee

1) This is up to the board designer.

2) Refer to the AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM.

3) This is up to the system designer (there is a possibility to embed hard-coded settings for the DDR controller into the firmware).

4) Refer to the AN5252 - QorIQ LS1046A Design Checklist.

5) I assume that any variant of termination is possible.

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1,468 Views
ufedor
NXP Employee
NXP Employee

> 4 such devices are directly connected to 64bit DDR4 controller of LS1046 and for ECC also

Is my understanding correct that total 5 identical SDRAM devices will be connected?

If "yes", then this is a typical recommended configuration - refer to the FRWYLS1046A-PA design:

https://www.nxp.com/design/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A#Design-Resou...

 

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1,454 Views
Urmila_123
Contributor II

Thanks for the reply sir!

All the 5 DDR4 devices used in FRWY-LS1046A-PA design are same? Can we know the part number of it?

 

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1,448 Views
ufedor
NXP Employee
NXP Employee

Please download the FRWY-LS1046A-PA Design files and open the BOM. 

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