DDR write leveling control for LX2160

[SamiraB]

Getting acquainted with the reference manual for the LX2160 SoC LX2160ARM, a suspicion crept in that there was a missing description of some registers. In particular, I did not find a description of the "DDR write leveling control". At the same time, it is mentioned on page 708.

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In the documentation for another processor, for example LS1046A LS1046ARM , with a similar memory controller, there is a description for DDR_WRLVL_CNTL, DDR_WRLVL_CNTL_2 and DDR_WRLVL_CNTL_3.

At the same time, the purpose and addresses of other registers are the same as in LX2160A. It makes one think that the LX2160A should also have some registers for write leveling control. The question is, do their addresses and fields match those for LS1046A or not?

Regards,
Samira

[kenli]

Who told u that ls1046 and lx2160 have the same DDR controller?

The DDR controller of LX2160 includes a PHY, and the training is done by the PHY itself. So it's normal that you can't see this register.