Code warrior can not connect to the bare board's CPU core----LS1043A

[weid]

Refer to the guide"Use CodeWarrior for ARMv8 to Debug U-boot and Linux Kernel and Bring up
Bare Boards ",we want to flash our bare board without changing the hardcode RCW, but fail,the fail log as flow:

Memory access failed.
//
Additional error details:
[Failed to write memory at address 0x2016002c on core CortexA53#0.
Core CortexA53#0 not found on the JTAG chain. Please verify that the Reset Configuration Word is correct, or enable RCW Override in the initialization file.]

the script config as flow:

USE_SAFE_RCW=True;

TA.rcw.set_source(0x9E);(determined by the board config-->SYSCLK = 100 MHz, single-ended)

the code warrior version is:Version: 11.5.0
Build Id: 200629GA

[LFGP]

you have to review the settings into the RCW initialization file, use the reference manual to check the values used for hard-coded RCW " 4.4.6.2 Hard-coded RCW options", also please review the steps, in the "CodeWarrior Development Studio for
QorIQ LS series - ARM V8 ISA, Targeting Manual", to override RCW through JTAG.

please take a note that " If a hard-coded RCW option is used, the user should not enable the core and the DDR controllers. The user may enable the core and DDR controllers after a valid RCW is restored."

[weid]

I've done what is in the guidebook and it still doesn't work;

[weid]

Hello, @LFGP
Thank you for your response；
I have checked the configuration of zhe board, it's as below:
cfg_rcw_src=0x25(rcw source is Nor flash)
system clock=100MHz, Single-ended；
The Reset_REQ_B signal is just pulled high through 4.7Kohm resistor；
The PORST_N and JTAG_RESET_N signal are connected together by wire and logic；

When the bare board come from factory（the Nor flash is blank), I want to program the flash by JTAG ,and do not change any Hardware(cfg_rcw_src);
I copy the script from code warrior tool(the script's name is LS1043A_RDB), and modify the USE_SAFE_RCW=True, TA.rcw.set_source(0x9E);
After done this,click the Flash Programmer button, then the script show fail；
I tried modifying the TA.rcw.set_source(0x9E) to 0X9F，0X9A and the script still fails；
Also, I found that ccs log prompt “Error message: LS1043A: Core not responding”

[LFGP]

the first step is to be sure that your DDR is supported by the SoC.
the second step is to check your CW License is active.
if all the above is ok then you need to add to CW a new algorithm for your flash device, please use the next link to download the application notes
https://community.nxp.com/t5/CodeWarrior-for-QorIQ/Adding-a-flash-device-configuration-CodeWarrior-1...

[weid]

The DDR is DDR4，3200MT/s，Microchip；
And the CW software version is 11.5，is an evaluation version license；

Is the failure of the script report in the Init_BRR() function and not yet in the DDRC initialization process（Init_DDRC() function）, is it also related to the memory configuration in this scenario?

[LFGP]

did you check if your NorFlash is listed in CW? if it isn't listed please follow the steps in the previous application note.
The error message "Core CortexA53#0 not found on the JTAG chain" is related to some problem in the MPU like power level, sysclock not stable or ""power sequence"", please be sure for this last one (you can find it in the data sheet).
Finally review the next kink to explain other method to bring up a Layerscape board.
https://www.nxp.com/docs/en/application-note/AN12270.pdf