One problem is fixed when I updated the ddr_get_ddr_params in ddr_init.c
The atf compiles now succesfully, but when I deploy it, I get
NOTICE: BL2: Built : 18:50:19, Feb 28 2026
NOTICE: Fixed DDR Config 1
ERROR: DDR Clk: MCLK cycle is 625 ps.
ERROR: DDR Clk is faster than DIMM can support.
ERROR: Execution FW failed (error code -5)
ERROR: Calculating DDR PHY registers failed.
The DIMM I am deploying is 2933Mhz (lower than the default 3200Mhz); I have already edited the RCW to lower the DDR controller to 2900 and even 2600. The error still happens.
How can I correctly configure the DDR clock?