Cache Locking on LS2080A/LS2085A

[renatomancuso]

Hello,

I was wondering if cache locking is available on any of the cache levels (L1, L2 or CPC) of the LS2080A or LS2085A platforms.

Also does this SoC include any performance monitoring unit similar to the EPU in QorIQ Pxxx platforms?

Thanks in advance for your answer.

[renatomancuso]

Great. Can the L3 also be configured as SRAM like in the P4080?

Thanks!

[Pavel]

Look at ARM community:

https://community.arm.com/thread/5122

The ARM Cortex-A57 does not support locking of the L1 or L2 cache, see these pages of the Technical Reference Manual:

ARM Cortex-A57 MPCore Processor Technical Reference Manual: 6.1. About the L1 memory system

ARM Cortex-A57 MPCore Processor Technical Reference Manual: 7.1. About the L2 memory system

Have a great day,
Pavel

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[renatomancuso]

Yes, I am aware of that. However, the LS208xA introduce a third level of cache. Does that level support locking?

[Pavel]

The LS208xA supports L3 cache locking.

Have a great day,
Pavel

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