Bus error interrupt on eTSEC DMA'ing

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Bus error interrupt on eTSEC DMA'ing

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romitchatterjee
Contributor V

I'm writing a Ethernet device driver for the LS1021A Tower board. Currently, I'm trying to use only eTSEC3 port with internal DMA and shared MDIO of eTSEC1. My interrupt handler is getting fired every time I try to do tx/rx with an EBERR error interrupt. I understand it is a bus error, but cannot figure out why it is occurring. I have already set up the TxBDs and RxBDs, as well as all the relevant registers (eTSEC3_TBDBPH, _RCTRL, DMACTRL etc.). I updated my code to use non-cacheable memory, but the behavior does not change. Is there something I'm missing during init/config? Do I need to do some SMMU3 related stuff (not doing any currently), like setting up the SCFG_MAC3_ICID and such?

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romitchatterjee
Contributor V

Thanks Platon,

That helped. I was actually setting the eTSECx_TBDBPH registers when they were not supposed to be. Removing that code made things work ok.

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romitchatterjee
Contributor V

Thanks Platon,

That helped. I was actually setting the eTSECx_TBDBPH registers when they were not supposed to be. Removing that code made things work ok.

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bpe
NXP TechSupport
NXP TechSupport

There are no reasons for EBERR other than bus errors. Note that
eTSEC DMA has no idea of the address translation done at MMU level,
so any pointers to memory in registers and BDs must be physical
addresses. Check RBPTR/TBPTR to see where the dedicated DMA

reads BDs, inspect the buffer pointed by the BDs at those addresses.

SMMU is disabled at reset, see the processor Reference
Manual, Section 9.4.8.1

Have a great day,
Platon

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