Built-in self test failed for DDR

[bhavani_y]

Hi,

we have a custom board designed based on LX2160ARDB with a discrete DDR on it.Our DDR4 RAM is of type K4A8G165WC-BCTD and has a max speed of 2666MT/s. Based on LSDK20.04 made below changes 

flexbuild/packages/firmware/atf/plat/nxp/soc-lx2160/lx2160ardb/platform_def.h

#define CONFIG_DDR_NODIMM

flexbuild/packages/firmware/atf/plat/nxp/soc-lx2160/lx2160ardb/ddr_init.c

struct dimm_params ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 2147483648u,
.capacity = 4294967296u,
.primary_sdram_width = 64,
.ec_sdram_width = 8,
.device_width = 16,
.die_density = 0x2,
.rdimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 16,
.n_col_addr = 10,
.bank_addr_bits = 0,
.bank_group_bits = 1,
.edc_config = 2,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 750,
.tckmax_ps = 1250,
.caslat_x = 0x000FF800,
.taa_ps = 13750,
.trcd_ps = 13750,
.trp_ps = 13750,
.tras_ps = 32000,
.trc_ps = 457500,
.twr_ps = 15000,
.trfc1_ps = 350000,
.trfc2_ps = 260000,
.trfc4_ps = 160000,
.tfaw_ps = 28000,
.trrds_ps = 6000,
.trrdl_ps = 7500,
.tccdl_ps = 5000,
.refresh_rate_ps = 7800000,
};

int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf)
{
static const char dimm_model[] = "Fixed DDR on board";

conf->dimm_in_use[0] = 1; /* Modify accordingly */
memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);

/* valid DIMM mask, change accordingly, together with dimm_on_ctlr. */
return 0x5;
}

Timings are modified based on the attached datasheet of DDR4.I have attached the boot log which contains the error details.we are not able to find which is causing DDR initialization failure.

Can anyone please help on this?

Thanks.

[zeeetor]

In ddr_init.c function dram_init， it seems that CONFIG_STATIC_DDR and CONFIG_DDR_NODIMM cannot exist simutaniously, so do you suggest use CONFIG_STATIC_DDR or CONFIG_DDR_NODIMM ?

[yipingwang]

When a board design uses fixed or discrete DDR, static timing can be used to configure DDR timing parameters.
Define macro “CONFIG_STATIC_DDR” in plat/nxp/<SOC>/<BOARD>/plafform_def.h to enable discrete DDR timings.
Define board_static_ddr() function and structure ddr_cfg_regs in file ddr_init.c.

Please refer to section "Discrete DDR" in LSDK user manual.

Please refer to definition "struct ddr_cfg_regs static_1600" in atf/plat/nxp/soc-lx2160/lx2160ardb/ddr_init.c.

You need to use QCVS DDRv tool to assist you to get the optimized and validated DDR controller configuration register values. You need to create a QCVS DDR project with the default configuration, then fill in "Properties" panel in this project according to DDR data sheet, then connect to the target board to do validation to get the optimized DDR controller configuration parameters to fill in structure ddr_cfg_regs.

[yipingwang]

1. Please refer to the attached description of Mock DIMM parameters, please fill "ddr_raw_timing" array in atf/plat/nxp/soc-lx2160/lx2160ardb/ddr_init.c according to your DDR data sheet, then program u-boot to the target board and boot up u-boot.

2. In CodeWarrior IDE, please create an QCVS DDR project with "reading from target" option in DDR configuration panel.

 3. In QCVS DDR project, please click "Validation" to use DDRv tool to do DDR validation and optimization.

 4. After validation with DDRv tool, please generate output file from Project->Generate Processor Expert code. And please refer to "uboot_ddr1.c" file to fill "static_1600" in atf/plat/nxp/soc-lx2160/lx2160ardb/ddr_init.c.