Hi,
we are using custom board based on ls1046ardb, only ddr is changed. This is old device which we are using and it is working fine and it is following the old PPA code flow. All are fine.
Now we are updating u-boot latest version with TF-A flow. we are getting the below error with debug enable in bl2 binary.
INFO: SoC workaround for Errata A008850 Early-Phase was applied
INFO: SoC workaround for Errata A010539 was applied
INFO: RCW BOOT SRC is QSPI
INFO: SoC workaround for DDR Errata A008511 was applied
INFO: SoC workaround for DDR Errata A009803 was applied
INFO: SoC workaround for DDR Errata A009942 was applied
INFO: SoC workaround for DDR Errata A010165 was applied
INFO: platform clock 400000000
INFO: DDR PLL1 1600000000
INFO: DDR PLL2 400000000
INFO: time base 8 ms
INFO: Parse DIMM SPD(s)
INFO: Controller 0
INFO: DIMM 0
INFO: addr 0x28
WARNING: tx_byte: nodev
WARNING: tx_byte: nodev
INFO: Invalid SPD at address 0x50
INFO: done with controller 0
ERROR: First slot cannot be empty.
ERROR: Parsing DIMM Error
ERROR: DDR init failed.
INFO: SoC workaround for Errata A008850 Post-Phase was applied
INFO: RCW BOOT SRC is QSPI
NOTICE: Incorrect DRAM0 size is defined in platform_def.h
ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:790
BACKTRACE: START: assert
I understand, we need to change the SPD ADDR, SPD BUS, the ddr timing, but I did change the SPD ADDR alone in atf code but no success, earlier we did change in u-boot old code, It was working. I am attaching that patch here. I think here the three points then it should work. One is changing the address, It should be 0x50, The I2C bus in our device is 1, but the default goes to 0 but I don't know where to change in atf code. Third one is ddr timing. We are using SPD EEPROM not static DDR., After seeing the patch, Please let me know where to change in atf and what to change about ddr timing.
PATCH START:
--------------------------------
--- x/board/freescale/ls1046ardb/ddr.h_ORIG 2020-06-03 16:01:40.246606100 +0000
+++ x/board/freescale/ls1046ardb/ddr.h 2020-06-03 16:02:03.304919580 +0000
@@ -29,10 +29,13 @@
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
- {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
+ {2, 2400, 0, 9, 7, 0x0805090C, 0x100D0F0B,},
+ // fallback
+ {1, 1000, 0, 8, 10, 0x0, 0x0,},
+ // WRLVL_CNTL=0x8675F607, SDRAM_CLK_CNTL=0x02400000 (big endian)
+ // WRLVL_START=WRLVL_CNTL[27:31]=00111 (7d); CLK_ADJUST=SDRAM_CLK_CNTL[5:9]=01001 (9d)
+ {1, 1700, 0, 9, 7, 0x0708080A, 0x090A0A09,},
+ {1, 2400, 0, 9, 7, 0x0708090B, 0x0B0C0C0A,},
{}
};
--- x/drivers/ddr/fsl/ddr4_dimm_params.c_ORIG 2020-06-03 16:01:49.557136472 +0000
+++ x/drivers/ddr/fsl/ddr4_dimm_params.c 2020-06-03 16:02:03.305919637 +0000
@@ -215,6 +215,7 @@
case DDR4_SPD_MODULETYPE_UDIMM:
case DDR4_SPD_MODULETYPE_SO_DIMM:
+ case 9: // ECC SO-DIMM ???
/* Unbuffered DIMMs */
if (spd->mod_section.unbuffered.addr_mapping & 0x1)
pdimm->mirrored_dimm = 1;
--- x/include/configs/ls1046ardb.h_ORIG 2020-06-03 16:01:59.456700379 +0000
+++ x/include/configs/ls1046ardb.h 2020-06-03 16:02:03.306919694 +0000
@@ -19,8 +19,8 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_DDR_SPD
-#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x50
+#define CONFIG_SYS_SPD_BUS_NUM 1
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
------------------------PATCH END-------------------
Please help me to get this, we are working on the bringup.
Thanks,
Gopi Krishna M
Lantronix
