ARM Cortex A57 and A53 L1/L2 cache error reporting
The attached patch adds error detection for A53 and A57 cores. Hardware error injection is supported on A53. Software error injection is supported on both.
For hardware error injection on A53 to work, proper access to L2ACTLR_EL1, CPUACTLR_EL1 needs to be granted by EL3 firmware. This is done by making an SMC call in the driver. Failure to enable access disables hardware error injection. For error interrupt to work, another SMC call enables access to L2ECTLR_EL1. Failure to enable access disables interrupt for error reporting.
CPU Memory Error Syndrome and L2 Memory Error Syndrome registers can be used for checking L1 and L2 memory errors. However, only A53 supports double-bit error injection to L1 and L2 memory. This driver uses the hardware error injection when available, but also provides a way to inject errors by software. Both A53 and A57 supports interrupt when multi-bit errors happen.
To use hardware error injection and the interrupt, proper access needs to be granted in ACTLR_EL3 (and/or ACTLR_EL2) register by EL3 firmware SMC call.
Correctable errors do not trigger such interrupt. This driver uses dynamic polling internal to check for errors. The more errors detected, the more frequently it polls. Combining with interrupt, this driver can detect correctable and uncorrectable errors. However, if the uncorrectable errors cause system abort exception, this driver is not able to report errors in time.
Build ATF and Kernel image with EDAC L1 and L2 cache error detection enabled in LSDK
In LLDPUG_RevL6.1.22_2.0.0 Yocto build environment, please rebuild ATF as the following.
$ source build_ls1043ardb/SOURCE_THIS
$ bitbake qoriq-atf -c cleansstate
$ bitbake qoriq-atf -c patch
Please go to atf source code folder build_ls1043ardb/tmp/work/ls1043ardb-fsl-linux/qoriq-atf/2.8+AUTOINC+atf-r0/git/, please apply patch 0001-Porting-helper-functions-for-EDAC-support-based-on-L.patch.
$ patch -p1 < 0001-Porting-helper-functions-for-EDAC-support-based-on-L.patch
And rebuild atf image.
$ bitbake qoriq-atf
Please rebuild Linux Kernel with the following commands.
$ source build_ls1043ardb/SOURCE_THIS
$ bitbake virtual/kernel -c cleansstate
$ bitbake virtual/kernel -c patch
Please go to Linux Kernel source code folder build_ls1043ardb/tmp/work/ls1043ardb-fsl-linux/linux-qoriq/6.1.y+gitAUTOINC+66e442bc7f-r0/git/ to apply patch 0001-drivers-edac-Add-L1-and-L2-error-detection-for-A53-a.patch.
$ patch -p1 < 0001-drivers-edac-Add-L1-and-L2-error-detection-for-A53-a.patch
$ bitbake virtual/kernel -c menuconfig
$ bitbake virtual/kernel
L1/L2 cache error detection and correction EDAC feature verification
root@localhost:~# dmesg | grep edac
[ 3.478641] EDAC DEVICE0: Giving out device to module edac-a53 controller cortex_edac_l1_l2: DEV edac-a53 (POLLED)
root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_sw_inject
root@localhost:~# [ 74.784912] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 count: 1 'Fatal error(s) on CPU 0
[ 74.784912] '
root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_hw_inject
[ 83.429371] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 count: 1 'Fatal error(s) on CPU 3
[ 83.429371] '
root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l2_ue_sw_inject
root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l2_ue_hw_inject
[ 106.985393] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 count: 1 'Fatal error(s) on CPU 0
[ 106.985393] '
[ 106.997164] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 count: 1 'Fatal error(s) on CPU 1
[ 106.997164] '
root@localhost:~# [ 115.232986] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 count: 1 'Fatal error(s) on CPU 0
[ 115.232986] '
root@localhost:~# dmesg | grep EDAC
[ 1.638675] EDAC MC: Ver: 3.0.0
[ 3.478641] EDAC DEVICE0: Giving out device to module edac-a53 controller cortex_edac_l1_l2: DEV edac-a53 (POLLED)
[ 74.784840] EDAC cortex_edac_l1_l2: CPU 0 L1-I Tag RAM error(s) detected
[ 74.784869] EDAC cortex_edac_l1_l2: CPU 0 L1 fatal error(s) detected (0x8000000080000000)
[ 74.784912] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 count: 1 'Fatal error(s) on CPU 0
[ 83.429298] EDAC cortex_edac_l1_l2: CPU 3 L1-D Data RAM error(s) detected
[ 83.429329] EDAC cortex_edac_l1_l2: CPU 3 L1 fatal error(s) detected (0x8000000089100010)
[ 83.429371] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 count: 1 'Fatal error(s) on CPU 3
[ 106.985331] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x80000000910dc138)
[ 106.985349] EDAC cortex_edac_l1_l2: CPU 1 L2 fatal error(s) detected (0x8000000080000000)
[ 106.985393] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 count: 1 'Fatal error(s) on CPU 0
[ 106.997164] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 count: 1 'Fatal error(s) on CPU 1
[ 115.232936] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x80000000910c0598)
[ 115.232986] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 count: 1 'Fatal error(s) on CPU 0
