CDL boot loader introduction The u-boot boot loader cannot be booted directly from the LPC32x0 boot ROM. Instead, a small loader program must be used to initialize the memory used by u-boot and then load it from it's non-volatile storage into memory before executing it. Because u-boot loads and executes from SDRAM, this initial loader must also initialize SDRAM. The CDL provides a reference boot loader called the kickstart loader that is meant to be the primary boot image loaded from the LPC3250 boot ROM. The kickstart loader can reside in NAND, NOR, or SPI FLASH and can be configured to load an image from any source into any address with any size. More information about the LPC32x0 boot process can be found on the LPC32x0 boot process page or in the LPC32x0 User's guide. The CDL has been ported to the Phytec, Embedded Artists, and Future Designs boards.   Kickstart loader and stage 1 definitions The terms kickstart loader and stage 1 application are used to describe the bootable images for the LPC32x0. A stage 1 application is the application we would ideally like to start when the LPC32x0 is reset or powered up. Stage 1 applications include programs such as u-boot, e-boot, or another full-featured application. Unfortunately, most stage 1 applications are too big to be directly booted by the LPC32x0 boot ROM. For systems where the stage 1 application can’t be directly booted, a smaller ‘kickstart’ boot loader is required to boot from the LPC32x0 boot ROM and then continue loading and start execution of the stage 1 application. For systems that boot from large block NAND FLASH or SPI FLASH, the maximum boot image size is 54K. If the application to be loaded exceeds this size or if the application needs to be loaded anywhere besides IRAM, the kickstart loader is required. The kickstart loader will in turn load the stage 1 application and transfer control to it after it has been loaded. If the application to be loaded is smaller than 54K and resides in IRAM, the stage 1 application can be directly loaded from the boot ROM instead of being routed through the kickstart loader. For systems that boot from small block NAND FLASH, the maximum boot image size is 15.5K. For systems that boot from NOR FLASH, no kickstart loader is needed (in most cases). The stage 1 application can be executed directly from NOR FLASH.   Kickstart loader The kickstart loader must be developed to be smaller than 54K (15.5K for systems that boot from small block NAND FLASH). This loader can include startup code that sets up the board’s initial GPIO states and muxes, setup the initial clocking, setup a basic MMU table if needed, setup all the memory interface, and then load an image and transfer control to that image. For small block NAND systems with the 15.5K boot image limit, this can be tough to manage. Tradeoffs may need to be made on what functions can be handled by the kickstart loader. Enabling all the functions may make a kickstart image that exceeds 15.5K. The image size would have to be reduced in this case by removing features from the kickstart loader and moving them to the stage 1 application. If your stage 1 application needs to execute in SDRAM, but the kickstart is too large with all the SDRAM init code, then code needs to be rearranged or aggressively optimized to meet the boot image size limitation.   Kickstart loader bootup procedure The following sequence shows how the LPC32x0 handles kickstart load and transfer from the boot ROM using NAND or SPI FLASH. LPC32x0 processor is reset LPC32x0 boot ROM interrogates boot devices For SPI FLASH, the image loaded at SPI FLASH offset 8 is loaded into IRAM at address 0x0 For NAND FLASH, the image loaded in page 1 of block 0 or 1 is loaded into IRAM at address 0x0 After the image is loaded, the boot ROM transfers control to the image’s startup code loaded at address 0x0   Stage 1 applications Stage 1 applications are applications that meet one of the following criteria: Loads and executes directly from the UART into IRAM Loads and executes from the kickstart loader in IRAM or SDRAM Loads and executes in place from NOR FLASH For Linux, u-boot can be considered a stage 1 application. For the Phytec and Embedded Artists boards, the kickstart loader loads S1L as the stage 1 application. S1L initializes the board functions such as clocking and SDRAM and then loads and starts u-boot. Optionally, the kickstart loader can use u-boot as the stage 1 application bypassing S1L. Stage 1 Loader The Stage 1 Loader (S1L) is an optional stage 1 application that provides debug, monitor, and boot support for an NXP micro controller. It can be used as the initial boot image the micro controller executes and then configured to load another image automatically. S1L is included free as part of the LPC32x0 CDL and is pre-installed on the Embedded Artist and Phytec LPC3250 based development boards. It can also be installed on Future Design LPC3250 based boards.The main features of the stage 1 loader are shown below: Register and memory change and dump Poke, peek, dump, fill Image load via a serial port , SDMMC card, or FLASH Supports raw binary and S-record files Images can be executed after loading Images can be saved in NAND FLASH NAND FLASH support Erase of NAND blocks Direct read and write of FLASH blocks and pages Bad block management MMU functions Data and instruction cache control Virtual address translation enable/disable Virtual address remapping Page table dump System support functions Baud rate control, clock control, system information Automatic load and run support Automatic load and execution of images from NAND FLASH, SDMMC, or via the terminal Testing functions SDRAM memory tests, bandwidth tests SDRAM calibration and configuration data   Other features of the CDL This CDL provides a generic set of drivers which highlight how specific peripherals and functions work. The CDL also provides Board Support Packages (BSP) for development boards based on the LPC32x0 microcontrollers. The BSPs provide reference code for system startup including boot loaders, system clock setup, SDRAM setup, and MMU/cache setup.The CDL provides the following features: Various drivers and header files for the LPC32x0 microcontroller Common software and definitions for LPC32x0 microcontrollers Support for Keil uVision4, ARM Realview 3.1, and GNU CodeSourcery tool chains BSPs for Embedded Artists, Phytec, and Future Designs LPC3250 based development boards A reference BSP for the NXP LPC32x0 based validation and reference platform A generic BSP that contains universal startup code for easy porting to a new LPC32x0 based platform Free for use with NXP LPC32x0 microcontrollers The Phytec, Embedded Artists, and Future Designs LPC3250 BSPs provide the following features: Startup code and board initialization code based on the board’s possible boot modes and devices Software to re-burn the boot loaders into NAND, SPI, or NOR FLASH Updated versions of the kickstart loader and S1L applications Tool-less software deployment options when used with the Stage 1 Loader or the Serial Loader Various peripheral examples that can downloaded and executed via S1L or a debugger Quickstart instructions The NXP LPC32x0 validation and reference platform is not commercially available, although the code included in the BSP is provided as part of the CDL. A generic LPC32x0 BSP is also provided as part of this CDL. This generic BSP provides the following features: Configurable startup code and board initialization code Standard and mobile single and double data rate SDRAM reference code based on the JEDEC SDRAM initialization sequence Reference drivers for small and large block NAND FLASH using the MLC and SLC controllers SPI FLASH and NOR FLASH reference drivers Burner software for burning and updating images in NAND, SPI, or NOR FLASH Various kickstart loader and S1L examples for multiple deployment methods Ideal for new board bringup (support for IRAM only boot via the Serial loader tool) Documentation that explains the reasoning and structure of the software

Introduction The MicroCore48/64/100 has been developed to evaluate, test and demonstrate general purpose Microcontrollers from NXP Semiconductors.  The Microcore48/64/100 demo, evaluation and test board supports NXP’s 100 pin (or less) Cortex M0/M0+/M3 based microcontrollers (LPC800, LPC1100, LPC1200, LPC1300, LPC1500 and LPC2100 family).  Special adapter boards are available to support a wide range of ARM Cortex based microcontrollers in different packages, like: LPC81x LPC111x, LPC11A1x, LPC11Cxx, LPC11E1x and LPC11Uxx LPC131x and LPC134x LPC151x and LPC154x   Main features of the MicroCore48/64/100 - Wide supply range of 0V to 3.6V    o Via primary USB (Vbus) 3.3V    o Via secondary USB (Virtual COMM Port) 3.3V    o Via pins (f.i lab supply) 0 - 3.6V - Additional supply of 1.8V available - Exchangeable external crystal - Every pin of the Microcontroller contains a measure point and jumpers to (dis)connect it from the on-board peripherals - Serial In-System Programming (ISP) is possible - One RS232 buffered serial communication interface is provided to connect the MicroCore48 to a PC (or terminal) - USB communication port interface is implemented    o Soft or hardware USB connect possibility - USB to serial (Virtual COMM port) interface is implemented - I2C bus I/O expander and 256 bytes EEPROM is implemented - SPI bus Real Time Clock with temperature sensor, watchdog, time stamp and internal crystal is implemented - SPI bus RF module for wireless communication is implemented - CAN bus interface is implemented - Digital IO is implemented    o 3 push buttons, one with RC network and one for external RESET    o 8 LED’s (connected to I2C I/O expander) - Analogue inputs to micro’s AD converter    o 10k potentiometer is implemented to divide the 3.3V Vdd    o Photo transistor for ambient light sensing   Functional Blocks NXP’s Microcontroller Central part of the MicroCore64 board is the microcontroller. It can be mounted directly (at the LQFP64 footprint), with a test socket from Yamaichi type: IC149-064-69-B5 or with the use of an adapter board placed over headers X1, X3, X5 and X7. Every pin of the micro contains a  measure point and a jumper (at X2, X4, X6 and X8). This allows the user to connect or disconnect every single pin from the on-board peripherals and power signals. RS232 The MicroCore64 contains a MAX3232CSE device and a 9-pin sub D connector for the RS232 interface between a PC (terminal emulator) and the on-chip UART of the microcontroller. The RS232 port can be directly connected to a PC COMx port with a standard serial cable, with a female 9 pin sub D connector. Note that jumpers J2 and J3 have to be set correctly. I2C The MicroCore64 kit also contains an NXP - PCA9500 I/O expander and 256 bytes EEPROM with I2C bus interface. The PCA9500's I2C address is determined by both a fixed on-chip mask address and by external hardware wired links on the MicroCore64. These hardware wired links are all grounded, resulting in an I2C device address for the IO expander of 0x40 and an I2C device address for the EEPROM of 0xA0 All (eight) I/O port pins are used to drive LEDs. These are also connected to pin header X11, to optionally connect the LEDs directly to port pins of the Microcontroller. SPI0 The MicroCore64 kit contains an NXP - PCF2129A device (RTC) with SPI interface, connected to the on-chip SSP0 interface of the microcontroller. SCK is connected to pin 41, SDI to pin 37 and SDO to pin 36. Chip Enable (Slave Select) is software controlled and connected to pin 34. The PCF2129A Interrupt output, Clock output and the Time Stamp input are available at 3 pin header P4. SPI1 The board contains a connector (X15) for an RFM12 module from Hope. This module is a low cost ISM band FSK transceiver module implemented with unique PLL. It works within signal ranges from 315/433/868/915MHZ bands and complies with FCC and ETSI regulations. The SPI interface, used to interface with a microcontroller for parameter settings, is connected to the on-chip SSP1 interface (if available). SCK is connected to pin 57, MOSI is connected to pin 51 and MISO is connected to pin 35. SS_RFM is connected to pin 49. The interrupt request output is connected to pin 50. For more info about the RFM12 module visit: http://www.hoperf.com/rf_fsk/cob/RFM12.htm. USB (device) Some micro’s like the LPC1347 and LPC11U24 do have an on-chip USB device controller. For that reason the board contains a USB interface to connect it to a host. Next to a USB type B connector a switch for the soft connect feature of the micro is provided (Q1 – PDTA114 plus yellow LED D10). VBUS of this interface can be used to supply power to the MicroCore64 (check J1). Power The Microcore64 board can be powered in three ways. Either using VBUS (5V) of one of the two USB connectors (jumper J1 to determine, see figure above), or directly (using a lab supply) at the center pin of J1 or at the 3V3 and GND header pins (P2 and P3). If powered over VBUS then green LED D1 indicates power present. To support LPC2100 parts an additional 1V8 supply is available at the board (P7).   XTAL The external crystal is mounted on a 3 pin female header (Y1). Middle pin is connected to GND for easy interchanging crystals or resonators. The load capacitors C4 and C5 can be replaced by other ones by unsoldering/soldering. USB (VCP) The board contains an FT232RL device from FTDI to provide a USB virtual com port interface between a host PC and the on-chip UART of the micro. Note that jumpers J2 and J3 have to be set correctly. VBUS2 can be used to power the MicoCore64. VBUS2 is also used to generate a 1V8 supply, available at P7. This supply is needed to support LPC2100 devices (like LPC2129). CAN bus Parts like the LPC2119 have an on-chip CAN interface. To support CAN the board contains a TJA1040 CAN transceiver and a 9 pin male sub D connector. To connect the CAN pins of the micro pin header P5 can be used. To bypass the transceiver (for example with an LPC11C24) pin header P6 can be used. Analog Inputs The MicroCore48 board contains a 10k potentiometer (R20) to provide an analog input to the micro. This input is available at pin 44 of the micro (AD1 input). A second analog input signal is generated by a photo transistor (Q2 - BPW85C) and is available at pin 45 of the micro (AD2 input). This input can be used as a light sensor. RESET, BOOT and WAKE UP The MicroCore64 contains three pushbuttons. S1 (plus RC network) used as RESET, S2 used as BOOT (to force the micro into ISP mode) and S3 connected to pin 53 of the micro (could for example be used to wake up the micro from a power reduction mode). LED Indicators Besides the eight red LEDs connected to the I2C IO expander the MicroCore64 contains two additional red LEDs (D11 and D12) connected to pin 14 and pin 15 of the microcontroller. SWD (Serial Wired Debug) The MicroCore64 is equipped with the commonly used 10 pin SWD connector. The debug interfaces from Keil uLink and IAR / Segger JLink can be used with this board. For evaluation of LPC2100 devices a separate JTAG connector is provided at the socket adapter board.

Description This example implements an audio interface class device mode device that enumerates as audio device (USB speakers) and sends the samples sent to it from the host to the audio circuitry on the board.   Compiler build configurations The software that makes up this example is designed to run on many different development boards. Therefore the compiler must be configured to build an image that is targeted to the development board you are using. This section explains how to set these build configurations for each of the supported compilers. NOTE: read the Design notes section below if you are running this example on a part that supports high speed controllers.   LPCXpresso IDE   Configure projects   right click on the BSP project in the project explorer window   click Build Configurations->Set Active->(see configuration in table below)   repeat these steps with the CDL, nxpUSBlib, and Example_AudioOutputDevice   Configure MCU   right click on the Example_AudioOutputDevice project in the project explorer window   click Properties->C/C++ Build->MCU settings->(see configuration in table below)   Configure the indexer    click Window->Preferences->C/C++->Indexer->Use active build configuration BSP CDL nxpUSBlib Example_AudioOutputDevice MCU LPC1850  / Hitex LPC18xx_HITEX LPC18xx LPC18xx_Device LPC18xx LPC1850 LPC4330  / Xplorer LPC4330_Xplorer LPC18xx LPC18xx_Device LPC18xx LPC4330 LPC4350  / Element14 LPC1435_ELEMENT14 LPC18xx LPC18xx_Device LPC18xx LPC4350 NOTE: The LPC18xx CDL is used with boards that hold LPC43xx parts. This is done because the LPC43xx CDL is currently experimental. The LPC18xx USB library is used because both parts share the same controller.   Keil uVision 4 IDE Configure a Batch Build     click on Project->Batch Build...   expand the BSP project to display a list of project targets   select the project target by checking the appropriate checkbox (see target list in table below)   repeat these steps with the CDL, nxpUSBlib_Device, and Example_AudioOutputDevice BSP CDL nxpUSBlib_Device Example_AudioOutputDevice LPC1850  / Hitex HITEX1800 LPC18xx LPC18xx_Device HITEX1800   Board connections and configurations   LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  older A2 design schematic ./BSP/schematics/HITEX_SCM_LPC1850EVA-A2-2.pdf   Connect the JTAG to the 20 pin receptacle marked X4 JTAG Connect the type-B end of a USB cable to the receptacle marked X2. Plug the type-A end of this cable into a PC Connect the mini-phono plug on a pair of headphones to the receptacle marked HP   LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  newer A4 design schematic ./BSP/schematics/HITEX_Final_LPC1850EVA-A3.pdf LPC4330_Xplorer (NGX Xplorer Evaluation Board with LPC4330) Connect the JTAG to the 10 pin receptacle marked J2 Connect the micro-b end of a USB cable to the receptacle marked USB0. Plug the type-A end of this cable into a PC Connect the mini-phono plug on a pair of headphones to the receptacle marked J5 LPC1435_ELEMENT14 (Element 14 gaming board with LPC4350) Connect the JTAG to the 10 pin receptacle marked J6 Connect one end of a type-A to type-A USB cable to the receptacle marked USB0. Plug the other end of this cable into a PC Connect the mini-phono plug on a pair of headphones to the receptacle marked J1 PC configuration Use a PC running Windows XP, Vista or 7 Connect the type-A end of the USB cable that is connected to the board into one of the USB receptacles on the PC Build and debug the example LPCXpresso IDE In the project explorer window of the IDE right click on the Example_AudioOutputDevice project and select Debug As->C/C++ MCU Application In the main window of the IDE click Run->Resume to start running the application   Keil uVision 4 IDE In the Batch Build window, select the project targets as described in Compiler Build Configurations and then click Build In the main window of the IDE click Debug->Start/Stop Debug Session click Debug->Run   How this example runs and what to look for On the PC select Control Panel->Hardware and Sound->Sound When the example is first run a new entry in the Sound dialog box will appear titled Speakers and have a description that reads "4-nxpUSBlib Audio Out Demo". Below this description should be the word Ready.   To test the audio output click on this entry in the Sound dialog box. Then click on the Configure button to bring up the Speaker Setup dialog box. In this box press the Test button. Sound should be played through the left side of your headphones first, then the right side. Design notes This example is designed to run only at full speed. The nxpUSBlib runs the USB controllers on the LPC18xx and LPC43xx parts at high speed by default. This default must be changed to run this example properly on these parts. To do this, change the value of the definition USB_FORCED_FULLSPEED in the file libraries/nxpusblib/nxpUSBlibConfig.h to 1

Introduction The IOH application examples provide a great and easy way to get started with I/O Handler. All provided IOH examples come with project files for LPCXpresso, Keil MDK and IAR EWARM. This page will give an overview on how to start exploring these examples. 1. Download the full IOH kit The first step is to download the full IOH kit. This kit contains: The IOH libraries. For every library one application note describing the library and the example application(s). One or more application example projects Download the full IOH kit attached Unzip the archive to e.g. C:/nxp/ 2. Open the project in the IDE The second step is opening the projects into the IDE. LPCXpresso: 1. Choose 'File'->'Import'. Then select 'General'->'Existing Projects into Workspace' 2. Select 'Select archive file' and click 'Browse'. Select the file 'lpcxpresso_nxp_lpcxpresso_11u37h.zip' which is in the unzipped folder       (e.g. C:/nxp/nxp_lpcxpresso_lpc11u37h_ioh/lpcxpresso_nxp_lpcxpresso_11u37h.zip) 3. Import all project into the workspace by clicking 'Finish'. Note: You may also choose to only import a selected number of projects. In that case, always                     make sure you import at least three project:      'lpc_chip_11uxx_lib', 'nxp_lpcxpresso_11u37h_board_lib' and the example project of interest. Keil MDK: In Keil, open the multi-project workspace located at: nxp_lpcxpresso_lpc11u37h_ioh\applications\lpc11xx\keil_uvision_projects\nxp_lpcxpresso_11u37h\nxp_lpcxpresso_11u37h_ioh_examples.uvmpw IAR EWARM: In IAR, open the multi-project workspace located at: nxp_lpcxpresso_lpc11u37h_ioh\applications\lpc11xx\iar_ewarm_projects\nxp_lpcxpresso_11u37h\nxp_lpcxpresso_11u37h_ioh_examples.eww 3. Building the project After successfullt importing the project into the IDE, the project can be build. LPCXpresso: Select the example project of interest and click the 'Build' icon. The chip and board project will be automatically be compiled. Keil MDK: 1. Right-click on the example of interest in the project explorer and select 'Choose as Active Project'. 2. Click 'Project'->'Batch Build...'. Select atleast the 'lib_lpc_chip_11uxx', 'lib_lpc_board_nxp_lpcxpresso_11u37h' and the project of interest. 3. Click 'Build'. IAR EWARM: 1. In the project explorer, select the project of interest from the drop-down list to make that project the active project. 2. Click 'Project'->'Batch build...' and then click 'Edit'. Select atleast the 'lib_lpc_chip_11uxx', 'lib_lpc_board_nxp_lpcxpresso_11u37h' and the project of interest as 'Configurations to build'. When done, press 'OK'. 3. Click 'Make'. Important: IAR EWARM may require an update and a patch. If this condition is not met, compilation (linking) will result in an 'internal error' message from the IAR linker. Please make sure you're running 6.70.1.5794 or higher and that you have installed the 'EWARM linker patch 6.70.2-5901'. Please check your IAR mypages for any available updates. 4. Flashing the binary into the board LPCXpresso: 1. Connect a USB cable to J6 of the LPC11U37H board. J6 is the Link-2 USB connector, which allows LPCXPresso to access the LPC11U37H target for programming and debugging. 2. Click the 'Debug' icon to launch a debug session. 3. click the 'Resume' icon to start code execution. Keil MDK: 1. Either: Configure the Link2 as CMSIS DAP/J-Link (click here for more details) and connect a USB cable to J6 of the LPC11U37H board. J6 is the Link-2 USB connector. Connect a supported external debugger to P1 2. Click the 'Load' icon in Keil to download the compiled binary into the board. 3. After download has finished, hit the reset button to run the example. IAR EWARM: 1. Either: Configure the Link2 as CMSIS DAP/J-Link (click here for more details) and connect a USB cable to J6 of the LPC11U37H board. J6 is the Link-2 USB connector. Connect a supported external debugger to P1 2. Click the 'Download and Debug' icon in IAR to download the compiled binary into the board and to start a debug session. 3. After download has finished, click the 'Go' icon to start code execution.

Introduction This page gives more detailed information on how to use the IOH libraries in custom projects when using the LPCXpresso IDE. For more general information regarding using IOH libraries in custom project or for detailed instructions for Keil MDK and IAR EWARM, visit IOH: Getting started with IOH in custom projects. Ready-to-use examples can be found at the main I/O Handler page. Note: This guide assumes the IOH I2S library is to be added to a project, hence the 'I2S' references. For other IOH libraries, 'I2S' should be replaced with the library name. 1. Add the IOH library (libioh_*lpcxpresso.a) to the project The first step is to configure the LPCXpresso project to link against the IOH library. Open the project properties. Browse to 'Settings', then 'Libraries'. Add the library name (minus the 'lib' prefix) to the first box ('Libraries (-l)'), the library location to the second box ('Library search path (-L)'). 2. Add the path where the library's header file resides to the project’s include path The next step is to add the file location of the library's header file to the include path of the project. Still in the project properties, browse to 'Settings', then 'Includes'. Add the location to the 'Include paths (-I)' box. 3. #include the IOH header file in the source code of the application The IOH header file must be included in the source code of the project (e.g. main.c) by using the following preprocessor directive: #include "IOH_I2S.h" 4. Configure the linker to place the IOH related sections in the IOH SRAM All IOH parts have an SRAM region reserved for I/O Handler. When starting IOH, usually by calling the library's init() function, I/O Handler expects this memory region to be loaded with the IOH data provided by the IOH library. This means this data must be stored in Flash and copied to the IOH SRAM upon startup. A convenient way to do this, is by using scatter loading. With scatter loading, the linker and c-library are instructed to program certain data sections (IOH data) into Flash, and copy it to the specifed region (IOH SRAM) upon start up. This requires a linker script. When using LPCXpresso, this is taken care of automatically when selecting an IOH-enabled part and using the 'Manage Linker Script' option active 5. Enable the IOH SRAM (SRAM1) before C-library initialization The copying of data from the 'load region' to the 'execution region' when using scatter loading (explained above) is executed by the c-library just before main() gets called. It's important that both regions are enabled when the copying is initiated. After power-on, the IOH SRAM on the LPC11E/U37H is disabled (clock disabled in the SYSAHBCLKCTRL register), so it must be enabled before the scatter loading is initiated. The startup file included in LPCXpresso for IOH-enabled parts automatically enable the SRAM in time. 6. Interact with IOH via the library's API The final step is to interact from the application with IOH. This can be done through the library's API. Each library comes with an application note explaining how to use the library and what data structures and functions are available, and with one or more application examples showing how to use the library. This application note and application example provide an easy way to get started. They can be downloaded from the main I/O Handler page.

Description This example implements a HID class device with mouse report descriptors. Mouse movement reports are sent to the host by the device when buttons or the joystick is pressed on the development board.   On the Embedded Artists LPCXpresso Rev A or B Baseboard this example will move the host PC's mouse cursor when the joystick is operated. Pressing the joystick down will create a mouse left click. Compiler build configurations The software that makes up this example is designed to run on many different development boards. Therefore the compiler must be configured to build an image that is targeted to the development board you are using. This section explains how to set these build configurations for each of the supported compilers.   LPCXpresso IDE Configure projects   right click on the BSP project in the project explorer window   click Build Configurations->Set Active->(see configuration in table below)   repeat these steps with the CDL, nxpUSBlib, and Example_MouseDevice Configure MCU   right click on the Example_MouseDevice project in the project explorer window   click Properties->C/C++ Build->MCU settings->(see configuration in table below) Configure the indexer    click Window->Preferences->C/C++->Indexer->Use active build configuration BSP CDL nxpUSBlib Example_MouseDevice MCU LPC1850  / Hitex LPC18xx_HITEX LPC18xx LPC18xx_Device LPC18xx LPC1850 LPC4330  / Xplorer LPC4330_Xplorer LPC18xx LPC18xx_Device LPC18xx LPC4330 LPC4350  / Element14 LPC1435_ELEMENT14 LPC18xx LPC18xx_Device LPC18xx LPC4350 LPC11U14 / LPCXpresso LPC11Uxx_LPCXpressoRevB LPC11Uxx LPC11Uxx_Device LPC11Uxx LPC11U14 LPC11U14 / MCB1000 LPC11u14_MCB1000 LPC11Uxx LPC11Uxx_Device LPC11Uxx LPC11U14 LPC1768  / MCB1700 LPC1768_MCB1700 LPC17xx LPC17xx_Device LPC17xx LPC1768 LPC1768  / LPCXpresso LPC17xx_LPCXpressoRevB LPC17xx LPC17xx_Device LPC17xx LPC1768 NOTE: The LPC18xx CDL is used with boards that hold LPC43xx parts. This is done because the LPC43xx CDL is currently experimental. The LPC18xx USB library is used because both parts share the same controller.   Keil uVision 4 IDE Configure a Batch Build     click on Project->Batch Build...   expand the BSP project to display a list of project targets   select the project target by checking the appropriate checkbox (see target list in table below)   repeat these steps with the CDL, nxpUSBlib_Device, and Example_MouseDevice BSP CDL nxpUSBlib_Device Example_MouseDevice LPC1850  / Hitex HITEX1800 LPC18xx LPC18xx_Device HITEX1800 LPC1768  / MCB1700 MCB1700 LPC17xx LPC17xx_Device MCB1700 LPC11U14 / MCB1000 MCB1000 LPC11Uxx LPC11Uxx_Device MCB1000   Board connections and configurations   LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  older A2 design schematic ./BSP/schematics/HITEX_SCM_LPC1850EVA-A2-2.pdf   Connect the JTAG to the 20 pin receptacle marked X4 JTAG Connect the type-B end of a USB cable to the receptacle marked X2. Plug the type-A end of this cable into a PC LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  newer A4 design schematic ./BSP/schematics/HITEX_Final_LPC1850EVA-A3.pdf   LPC4330_Xplorer (NGX Xplorer Evaluation Board with LPC4330) Connect the JTAG to the 10 pin receptacle marked J2 Connect the micro-b end of a USB cable to the receptacle marked USB0. Plug the type-A end of this cable into a PC   LPC1435_ELEMENT14 (Element 14 gaming board with LPC4350) Connect the JTAG to the 10 pin receptacle marked J6 Connect one end of a type-A to type-A USB cable to the receptacle marked USB0. Plug the other end of this cable into a PC   LPC11u14_MCB1000 (Keil MCB1000 development board) schematic: ./BSP/schematics/mcb1000-schematics.pdf   Jumpers:   J4 = 2-3      (UCON - PIO0_6 pulls D+ high)   J2 = 1-2          (VDD  - core power)   J5 not installed  (ISP  - ISP via COMM)   J6 not installed  (RST  - ISP via COMM) Connect the JTAG debugger to the 10 pin Cortex Debug connector labeled J3 Connect the type-B end of a USB cable to the type-B recepticle and the type-A end of the cable to the USB receptacle on a PC Once the USB cable is connected to the board the following LEDs should be illuminated:     Power     All 8 LEDs in PIO2   LPC1768_MCB1700 (Keil MCB1700 development board) schematic: ./BSP/schematics/mcb1700-schematics.pdf   Jumpers:   E/U    = 1-2  (Ethernet/USB)   UMODE  = 1-2  (USB Device Mode)   D-     = Device   D+     = Device   VBUS   = 1-2   VDDIO  = 1-2   VDDREG = 1-2   Connect the JTAG debugger to the 20 pin JTAG or 10 pin Cortex Debug connector. Connect the type-B end of a USB cable to the type-B recepticle labeled 'Device' and the type-A end of the cable to the USB receptacle on a PC. Once the USB cable is connected to the board the following LEDs should be illuminated:     Power     100MHz     USC (LED indicates a USB soft connect from P2.9)    LPC11Uxx_LPCXpressoRevB (LPCXpresso LPC11Uxx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/lpcxpresso.lpc11u14.schematic.pdf   Running this example on the LPCXpresso LPC11U14 can be done one of two ways:   1. LPCXpresso LPC11U14 stand-alone       Connect the type-B end of a USB cable to the mini receptacle on the LPCXpresso board labeled J8 and the type-A end to the USB receptacle on a PC   2. LPCXpresso LPC11U14 plugged into the LPCXpresso base board Rev B       Plug the LPCXpresso LPC11U14 board into the connector labeled J4 on a LPCXpresso base board Rev B       Configure the base board according to the user's guide from Embedded Artists       Connect the mini type-B end of a USB cable to the receptacle on the base board labeled X1 and the type-A end to the USB receptacle on a PC       Once the USB cable is connected to the board the following LEDs should be illuminated:           LED25  (vbus)          LED26  (3.3v rail)         For both configurations the JTAG debugger is connected to the mini USB receptacle labeled J3 on the LPCXpresso LPC11U14 board   LPC17xx_LPCXpressoRevB (LPCXpresso LPC17xx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/LPCXpressoLPC1769revB.pdf   Running this example on the LPCXpresso LPC1769 can be done one of two ways:   1. LPCXpresso LPC1769 stand-alone. Solder a type-B USB receptacle onto the board and wire it up. See included schematics for details. Connect the type-B end of a USB cable to the receptacle on the LPCXpresso board and the type-A end to the USB receptacle on a PC   2. LPCXpresso LPC1769 plugged into the LPCXpresso base board Rev B. Plug the LPCXpresso LPC1769 board into the connector labeled J4 on a LPCXpresso base board Rev B. Configure the base board according to the users guide from Embedded Artists. Connect the mini type-B end of a USB cable to the receptacle on the base board labeled X1 and the type-A end to the USB receptacle on a PC.    Once the USB cable is connected to the board the following LEDs should be illuminated:       LED25  (vbus)       LED26  (3.3v rail)         For both configurations the JTAG debugger is connected to the mini USB receptacle labeled J3 on the LPCXpresso LPC1769 board.   PC configuration Use a PC running Windows XP, Vista or 7 Connect the type-A end of the USB cable that is connected to the board into one of the USB receptacles on the PC Build and debug the example LPCXpresso IDE In the project explorer window of the IDE right click on the Example_MouseDevice project and select Debug As->C/C++ MCU Application In the main window of the IDE click Run->Resume to start running the application   Keil uVision 4 IDE In the Batch Build window, select the project targets as described in Compiler Build Configurations and then click Build In the main window of the IDE click Debug->Start/Stop Debug Session click Debug->Run   How this example runs and what to look for When the example is run and the board is connected to a PC with a USB cable it will enumerate on the PC as a HID Mouse device. You should see the device appear in the "Device Manager" under "Mice". If you right click on HID  Device->Properties a window will appear called "HID Mouse Device Properties". If you select the "Details" tab you will see a "Properties" drop down, click on it and select "Hardware Ids". You should see the below entries for Vendor Id and Product Id.   HID\VID_1FC9&PID_2041&REV_0001 HID\VID_1FC9&PID_2041   This information should match the data in the "Device Descriptor Structure" in the "Descriptors.c" file in the Example_MouseDevice project directory.   Press the joystick to move the mouse cursor on the PC desktop and push the buttons to cause mouse buttons to click.

Before you can use the MLC extractor tool (MET), you need to customize it for your hardware and rebuild it. You will need the CodeSourcery GNU toolchain (EABI version) to build the files. Download the CodeSourcery toolchain from here. A free 'lite' version is available that can be used to build the MET. Install the tools and make sure the PATH environment variable for the tools is setup correctly. MET relies on the Common Driver Library (CDL) for some of it's functions, so the LPC32x0 CDL (v2.11 and later) must be downloaded and installed first. You can download the CDL from here. Once the CDL is downloaded, install it by extracting the directory somewhere on your Windows XP/Vista/7 machine. Download the MET file from this page and extract the contents into the CDL directory from the step above. The file must specifically be extracted in the ./csps/lpc32x0/bsps/common/examples directory. The most likely change needed to the source code is adding a specific NAND device to the NAND detection list. In the mlc_fgen_tool folder in the ./csps/lpc32x0/bsps/common/examples directory, edit the nandif.c file and locate the sys_nand_ids structure. This structure contains a list of recognized NAND IDs with geometry for each ID. This list is self-explanatory - either edit an existing entry in the list or add a new entry in the list with the new NAND information. <code>   /* ST MICRO Flash */   {     LPCNAND_VENDOR_STMICRO,     0x73, /* Device ID */     512, /* Page size */     32, /* Pages per block */     1024, /* Total blocks */     {SLCNAND_DEFAULT_TIMING, MLCNAND_DEFAULT_TIMING},/* Timing */   } <code> You can rebuild the code with the steps below. First, open a Windows 'cmd' shell and switch to the CDL directory. Use the "setenv" command to setup the environment for build. Note the 2nd parameter (board) doesn't matter, so we'll use "ohy3250". The 3rd parameter is the toolchain which will be ""gnu". The 4rth parameter is "1", indicating verbose output. Switch to the mlc_fgen_tool directory and type "make". If the tools are installed and everything is setup correctly, the tool will build and you will get a "mlcextractor.bin" file that can be used with the serial loader tool.

Build procedures Open the M0 and M4 projects by clocking on the uvproj files. Make sure the 'iram' version of the project is selected in the target seleciton window. Select the Build target item from the Project menu to build the images. Build the M0 version of the project first, as the M0 binary is used for the M4 version. The FLASH version of the project works the same way as the IRAM version, but runs out of FLASH while using IRAM for RW data. When building the FLASH version, make sure both the M0 and M4 binaries are built using the FLASH configuration. Build the M0 version first, and then the M4 version. The BOOT1 to BOOT4 jumpers on the Hitex board should be setup as BOOT1-1-2, BOOT2-2-3, BOOT3-2-3, and BOOT4-1-2. Opened M0 project shown below Opened M4 project shown below Start the debug session Connect the Keil ULink2 JTAG debugger to the Hitex LPC4350 board's 10-pin JTAG connector. Power up the board by plugging in a 5.0v supply into the power plug (X14). On my board, the boot configuration was set as follows: BOOT1-1-2, BOOT2-2-3, BOOT3-2-3, BOOT4-2-3. Make sure the JTAG is setup correctly for dual-core debugging. In the M4 project window, select the Start/stop Debug Session item from the debug menu to load the image into the board. The image should load and run until the main() function. At this point, you can select run from the debug menu to start the M4 core. The M4 core will initialize the system and board and boot the M0 core. Both the M0 and M4 core will be running FreeRTOS and the red, blue, and green LEDs will start blinking. Let the M4 core run for a few seconds and then select stop from the debug menu. The red LED will stop blinking (indicating the M4 core is stopped), while the blue and green LEDs will continue blinking. After a short time, the green LED will quit blinking and only the blue LED will blink. The green LED is controlled by the shared memory queue the M4 core populates. When the M4 core was stopped, the filling of the queue on the M4 side was stopped, so the M0 core continued processing what was left in the queue until it ran out on entries. Restart the M4 core and both the red and green LEDs will start blinking again. Stop the M4 core and wait until the green LED stops blinking. Leave the M4 core stopped and switch to the M0 project. Select Start/stop Debug Session item from the debug menu to connect to the running process. The M0 core will stop once you do this. Make absolutely sure that the debug options for loading the image into memory or altering system configuration via the linker init file are dsiabled, as we don't want to reload and restart the process that was kicked off from the M4 core. At this point, both the M0 and M4 debug sessions are halted. You can start and stop or single step via each session independently! Select run from the M0 or M4 sessions' debug menu to restart only that core. Depending on which core you've started, the red or blue LED (and possibly green for the M0 core if the queue has data) will start blinking. You can view the state of shared memory queue in real-time by opening a memory window and typing in the address 0x10080000. You'll see the M4 and M0 indexes incrementing.

Introduction This page gives more detailed information on how to use the IOH libraries in custom projects when using the IAR EWARM IDE. For more general information regarding using IOH libraries in custom project or for detailed instructions for LPCXpresso and Keil, visit IOH: Getting started with IOH in custom projects. Ready-to-use examples can be found at the main I/O Handler page. Note: This guide assumes the IOH I2S library is to be added to a project, hence the 'I2S' references. For other IOH libraries, 'I2S' should be replaced with the library name. 1. Add the IOH library (ioh_*_iar.a) to the project The first step is to configure the IAR project to link against the IOH library. This can be done by simply adding the .a file to the project. 2. Add the path where the library's header file resides to the project’s include path The next step is to add the file location of the library's header file to the include path of the project. Open the project options and browse to the category 'C/C++ Compiler', then to the tab 'Preprocessor'. Add the location of the header file to the 'Additional include directories'. 3. #include the IOH header file in the source code of the application The IOH header file must be included in the source code of the project (e.g. main.c) by using the following preprocessor directive: #include "IOH_I2S.h" 4. Configure the linker to place the IOH related sections in the IOH SRAM All IOH parts have an SRAM region reserved for I/O Handler. When starting IOH, usually by calling the library's init() function, I/O Handler expects this memory region to be loaded with the IOH data provided by the IOH library. This means this data must be stored in Flash and copied to the IOH SRAM upon startup. A convenient way to do this, is by using scatter loading. With scatter loading, the linker and c-library are instructed to program certain data sections (IOH data) into Flash, and copy it to the specifed region (IOH SRAM) upon start up. This requires a linker script. The linker script can be added to the IARproject by opening the projects options and browsing to the 'Linker' category. First check the 'Override default' checkbox, then add the file location to the 'Linker configuration file' box. Following is the part of the linker script used for the LPC11U37H, responisble for placing the IOH sections in the SRAM1 region (IOH SRAM): define symbol __IOHRAM_start__ = 0x20000000; define symbol __IOHRAM_end__   = 0x200007FF; define region IOHRAM_region = mem:[from __IOHRAM_start__ to __IOHRAM_end__]; initialize by copy { section .ioh_text }; initialize by copy { section .ioh_constdata }; initialize by copy { section .ioh_data }; place in ROM_region { section .ioh_text_init }; place in ROM_region { section .ioh_constdata_init }; place in ROM_region { section .ioh_data_init }; place in IOHRAM_region { rw section .ioh_text}; place in IOHRAM_region { rw section .ioh_constdata }; place in IOHRAM_region { rw section .ioh_data }; place in IOHRAM_region { rw section .ioh_bss }; 5. Enable the IOH SRAM (SRAM1) before C-library initialization The copying of data from the 'load region' to the 'execution region' when using scatter loading (explained above) is executed by the c-library just before main() gets called. It's important that both regions are enabled when the copying is initiated. After power-on, the IOH SRAM on the LPC11E/U37H is disabled (clock disabled in the SYSAHBCLKCTRL register), so it must be enabled before the scatter loading is initiated. The right place (assuming the CMSIS standard is followed) to enable the IOH SRAM, is in the SystemInit function. SystemInit() is called just before the C-enviroment is initialized as can been seen from the following snippet from the LPC11xx IAR startup file: PUBWEAK Reset_Handler SECTION .text:CODE:REORDER(2) Reset_Handler LDR     R0, =SystemInit BLX     R0 LDR     R0, =__iar_program_start BX      R0 Therefore the SystemInit() function should contain the code for enabling the IOH SRAM block, e.g. by adding the following line to the SystemInit() function (assuming the LPC11E/U37H): LPC_SYSCON->SYSAHBCLKCTRL |= (1<<26); 6. Interact with IOH via the library's API The final step is to interact from the application with IOH. This can be done through the library's API. Each library comes with an application note explaining how to use the library and what data structures and functions are available, and with one or more application examples showing how to use the library. This application note and application example provide an easy way to get started. They can be downloaded from the main I/O Handler page.

The LPC32x0 boots from SPI FLASH first, NOR FLASH second, and NAND FLASH last. The LPC32x0 will always attempt to boot from the first valid boot source based on a special boto pattern located at the start of the FLASH device. If you need to erase one of these FLASH boot sources, the procedure below can be used. Step 1: Download the pre-built boot software and restoration images for the Phytec LPC3250 board from the Resource page. Step 2: Extract the files on a Windows based PC Step 3: Connect a serial cable between the Phytec boards' lower serial connector and the PC Step 4: Start the Serial loader software (LPC3250_Loader.exe) included in the pre-built boot software package. Step 5: Setup the 'Primary boot (IRAM)' file in the Serial loader to one of the eraser binary image files. To erase NOR FLASH, use the eraser_nor_rvw.bin file. For SPI FLASH, use the eraser_spi_rvw.bin file. For NAND FLASH, use the eraser_sb_nand_rvw.bin file. Verify that the Comport control selection matches the COM part on the PC that is connected to the Phytec board. The example below shows the configuration for erasing NOR FLASH. NOTE: The pre-built binaries may have slightly different names than those listed in step 5, depending on the tool used to build the binaries. If the binaries were build with GNU instead of Realview, the 'rvw' field in each name will contain the 'gnu' identified instead. Change the file names as necessary for you binaries you have.

This procedure explains how to install and update u-boot on the EA1788 board. The install procedure requires 'Flash Magic' to place the initial image in internal FLASH, but once the image is in FLASH, it can be updated via u-boot itself. 1)Get the Flash Magic software at http://www.flashmagictool.com/ and install it. 2)Connect the serial UART on the EA1788 board to your Windows PC with the installed Flash Magic software. 3)On the EA1788 board, hold down the SW6 button while resetting the board to put it in ISP mode. 4)Download the program (u-boot-lpc.hex) via Flash Magic (see configuration below). It takes about 3 minutes to download. 5)Close Flash Magic and open a terminal program )ie, Teraterm) and configure it for 115.2K8N1 on the EA1788's connected UART. 6)Reset the board and you should get the UART prompt. U-Boot 2011.06 (Aug 16 2011 - 16:47:50) NXP LPC1788 Cortex-M3 DRAM:  32 MiB Flash: 512 KiB NAND:  128 MiB Bad block table found at page 65472, version 0x01 Bad block table found at page 65408, version 0x01 In:    serial Out:   serial Err:   serial uboot> 7)To update u-boot, download the u-boot-lpc.bin program via serial port or network and update with the procedure below. The procedure below uses tftp. Err:   serial uboot> dhcp BOOTP broadcast 1 DHCP client bound to address 10.1.10.14 TFTP from server 10.1.10.15; our IP address is 10.1.10.14 Filename 'u-boot-lpc.bin'. Load address: 0xa0100000 Loading: ######################### done Bytes transferred = 125580 (1ea8c hex) uboot> erase bank 1 Erase Flash Bank # 1 Erasing 30 sectors starting at sector  0. uboot> cp.b 0xa0100000 0x0 0x1f000 Copy to Flash... Writing 126976 bytes from a0100000 from 0, please be patient... done uboot> cmreset resetting ... U-Boot 2011.06 (Aug 16 2011 - 15:38:33) NXP LPC1788 Cortex-M3 DRAM:  32 MiB Flash: 512 KiB NAND:  128 MiB Bad block table found at page 65472, version 0x01 Bad block table found at page 65408, version 0x01 In:    serial Out:   serial Err:   serial uboot>

Description This example implements a mass storage class host mode device that enumerates a mass storage class device (USB flash drive). It reads the first sector of the device and displays a hexdump style listing of that data on a terminal.   Compiler build configurations The software that makes up this example is designed to run on many different development boards. Therefore the compiler must be configured to build an image that is targeted to the development board you are using. This section explains how to set these build configurations for each of the supported compilers.   LPCXpresso IDE Configure projects   right click on the BSP project in the project explorer window   click Build Configurations->Set Active->(see configuration in table below)   repeat these steps with the CDL, nxpUSBlib, and Example_MassStorageHost Configure MCU   right click on the Example_MassStorageHost project in the project explorer window   click Properties->C/C++ Build->MCU settings->(see configuration in table below) Configure the indexer    click Window->Preferences->C/C++->Indexer->Use active build configuration   BSP CDL nxpUSBlib Example_MassStorageDevice MCU LPC1850  / Hitex LPC18xx_HITEX LPC18xx LPC18xx_Host LPC18xx LPC1850 LPC4330  / Xplorer LPC4330_Xplorer LPC18xx LPC18xx_Host LPC18xx LPC4330 LPC4350  / Element14 LPC1435_ELEMENT14 LPC18xx LPC18xx_Host LPC18xx LPC4350 LPC1768  / MCB1700 LPC1768_MCB1700 LPC17xx LPC17xx_Host LPC17xx LPC1768 LPC1768  / LPCXpresso LPC17xx_LPCXpressoRevB LPC17xx LPC17xx_Host LPC17xx LPC1768 NOTE: The LPC18xx CDL is used with boards that hold LPC43xx parts. This is done because the LPC43xx CDL is currently experimental. The LPC18xx USB library is used because both parts share the same controller. Keil uVision 4 IDE Configure a Batch Build     click on Project->Batch Build...   expand the BSP project to display a list of project targets   select the project target by checking the appropriate checkbox (see target list in table below)   repeat these steps with the CDL, nxpUSBlib_Host, and Example_MassStorageDevice BSP CDL nxpUSBlib_Host Example_MassStorageDevice LPC1850  / Hitex HITEX1800 LPC18xx LPC18xx_Host HITEX1800 LPC1768  / MCB1700 MCB1700 LPC17xx LPC17xx_Host MCB1700   Board connections and configurations LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  older A2 design schematic ./BSP/schematics/HITEX_SCM_LPC1850EVA-A2-2.pdf Connect the JTAG to the 20 pin receptacle marked X4 JTAG Connect a USB flash drive into the type A receptacle marked X10 Connect a 9-pin serial cable into the receptacle marked UART X1. Connect the other end of this cable into a PC running a terminal program. To power the board:   Connect the type-B end of a powered USB cable into the receptacle marked X13   or   Supply 5v to the DC connector labeled X14   LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  newer A3 design schematic ./BSP/schematics/HITEX_Final_LPC1850EVA-A3.pdf   LPC1768_MCB1700 (Keil MCB1700 development board) schematic: ./BSP/schematics/mcb1700-schematics.pdf Jumper Setting   E/U 1-2 UMODE 1-2 D- Host D+ Host VBUS 1-2 VDDIO 1-2 VDDREG 1-2 ISP removed Connect the JTAG debugger to the 20 pin JTAG or 10 pin Cortex Debug connector Connect a 9 pin serial cable between COM0 on the board and a PC running a terminal program. Baud rate = 9600 Plug a USB flash drive into the type A receptacle marked HOST To power the board:   Connect the type-B end of a powered USB cable to the type-B receptacle labeled 'Device'   or   Supply 5v to the -VIN+ pins between the JTAG and COM0 receptacles Once the board is powered the following LEDs should be illuminated:     Power     100MHz     USC   LPC17xx_LPCXpressoRevB (LPCXpresso LPC17xx on the LPCXpresso Rev B base board) schematic: ./BSP/schematics/LPCXpressoLPC1769revB.pdf   Plug the LPCXpresso LPC1769 board into the connector labeled J4 on a   LPCXpresso base board Connect the JTAG to the mini USB receptacle labeled J3 on the LPCXpresso LPC1769   board Configure the base board according to the users guide from Embedded Artists Install jumpers 1-2, 3-4, 5-6 on the jumper block marked J61 on the base board Plug a USB flash drive into the type A receptacle marked J60 on the base board Connect the mini type-B end of a USB cable to the USB-to-serial receptacle on   the base board labeled X3 and the type-A end to the USB receptacle on a PC. Once the USB cable is connected to the board the following LEDs should be   illuminated:     LED25  (vbus)     LED26  (3.3v rail)          PC configuration Use a PC running Windows XP, Vista or 7 to display runtime diagnostics that can be viewed with a terminal emulation program like Teraterm or Hyperterm. The baud rate in these programs should be set to 9600.   Build and debug the example LPCXpresso IDE In the project explorer window of the IDE right click on the Example_MassStorageHost project and select Debug As->C/C++ MCU Application In the main window of the IDE click Run->Resume to start running the application   Keil uVision 4 IDE In the Batch Build window, select the project targets as described in Compiler Build Configurations and then click Build In the main window of the IDE click Debug->Start/Stop Debug Session click Debug->Run   How this example runs and what to look for When the example is first run the terminal window will display: Mass Storage Host Demo running.   When a flash drive is plugged in the terminal window will display   something similar to this:   Device Attached.   Total LUNs: 1 - Using first LUN in device. Vendor "USB     ", Product "Flash Disk      " Mass Storage Device Enumerated.   Waiting until ready...   Retrieving Capacity...   1957887 blocks of 512 bytes.   Contents of first block:   33 C0 8E D0 BC 00 7C FB 50 07 50 1F FC BE 1B 7C     3.....|.P.P....| BF 1B 06 50 57 B9 E5 01 F3 A4 CB BD BE 07 B1 04     ...PW........... 38 6E 00 7C 09 75 13 83 C5 10 E2 F4 CD 18 8B F5     8n.|.u.......... 83 C6 10 49 74 19 38 2C 74 F6 A0 B5 07 B4 07 8B     ...It.8,t....... F0 AC 3C 00 74 FC BB 07 00 B4 0E CD 10 EB F2 88     ..<.t........... 4E 10 E8 46 00 73 2A FE 46 10 80 7E 04 0B 74 0B     N..F.s*.F..~..t. 80 7E 04 0C 74 05 A0 B6 07 75 D2 80 46 02 06 83     .~..t....u..F... 46 08 06 83 56 0A 00 E8 21 00 73 05 A0 B6 07 EB     F...V...!.s..... BC 81 3E FE 7D 55 AA 74 0B 80 7E 10 00 74 C8 A0     ..>.}U.t..~..t.. B7 07 EB A9 8B FC 1E 57 8B F5 CB BF 05 00 8A 56     .......W.......V 00 B4 08 CD 13 72 23 8A C1 24 3F 98 8A DE 8A FC     .....r#..$?..... 43 F7 E3 8B D1 86 D6 B1 06 D2 EE 42 F7 E2 39 56     C..........B..9V 0A 77 23 72 05 39 46 08 73 1C B8 01 02 BB 00 7C     .w#r.9F.s......| 8B 4E 02 8B 56 00 CD 13 73 51 4F 74 4E 32 E4 8A     .N..V...sQOtN2.. 56 00 CD 13 EB E4 8A 56 00 60 BB AA 55 B4 41 CD     V......V.`..U.A. 13 72 36 81 FB 55 AA 75 30 F6 C1 01 74 2B 61 60     .r6..U.u0...t+a` 6A 00 6A 00 FF 76 0A FF 76 08 6A 00 68 00 7C 6A     j.j..v..v.j.h.|j 01 6A 10 B4 42 8B F4 CD 13 61 61 73 0E 4F 74 0B     .j..B....aas.Ot. 32 E4 8A 56 00 CD 13 EB D6 61 F9 C3 49 6E 76 61     2..V.....a..Inva 6C 69 64 20 70 61 72 74 69 74 69 6F 6E 20 74 61     lid partition ta 62 6C 65 00 45 72 72 6F 72 20 6C 6F 61 64 69 6E     ble.Error loadin 67 20 6F 70 65 72 61 74 69 6E 67 20 73 79 73 74     g operating syst 65 6D 00 4D 69 73 73 69 6E 67 20 6F 70 65 72 61     em.Missing opera 74 69 6E 67 20 73 79 73 74 65 6D 00 00 00 00 00     ting system..... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00     ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00     ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00     ................ 00 00 00 00 00 2C 44 63 18 2E 07 C3 00 00 80 01     .....,Dc........ 01 00 06 20 00 77 00 02 00 00 00 DE 1D 00 00 00     ... .w.......... 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00     ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00     ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 AA     ..............U.   When the flash drive is unplugged the ternimal window will display: Device Unattached.

Description This example implements an audio interface class host mode device that enumerates an audio interface class device (USB speakers) and sends samples to the device. The samples are created by a simple square wave generator in a timer ISR and shipped out the streaming isochronous output pipe when a button is pressed on the board. Getting started This example can be built and debugged using two compiler tool chains. Visit http://www.lpcware.com/content/project/nxpusblib/build-it to learn how to setup and configure these tool chains to build this example. Compiler build configurations The software that makes up this example is designed to run on many different development boards. Therefore the compiler must be configured to build an image that is targeted to the development board you are using. This section explains how to set these build configurations for each of the supported compilers. LPCXpresso IDE Configure projects   right click on the BSP project in the project explorer window   click Build Configurations->Set Active->(see configuration in table below)   repeat these steps with the CDL, nxpUSBlib, and Example_AudioOutputHost Configure MCU   right click on the Example_AudioOutputHost project in the project explorer window   click Properties->C/C++ Build->MCU settings->(see configuration in table below) Configure the indexer   click Window->Preferences->C/C++->Indexer->Use active build configuration BSP CDL nxpUSBlib Example_AudioOutputHost MCU LPC1850  / Hitex LPC18xx_HITEX LPC18xx LPC18xx_Host LPC18xx LPC1850 Keil uVision 4 IDE Configure a Batch Build   click on Project->Batch Build...   expand the BSP project to display a list of project targets   select the project target by checking the appropriate checkbox     (see target list in table below)   repeat these steps with the CDL, nxpUSBlib_Device, and Example_AudioOutputHost BSP CDL nxpUSBlib_Host Example_AudioOutputHost LPC1850  / Hitex HITEX1800 LPC18xx LPC18xx_Host HITEX1800 Board connections and configurations LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  older A2 design schematic ./BSP/schematics/HITEX_SCM_LPC1850EVA-A2-2.pdf Connect the JTAG to the 20 pin receptacle marked X4 JTAG Plug USB speakers into the type A receptacle marked X10 Connect a 9-pin serial cable into the receptacle marked UART X1. Connect the other end of this cable into a PC running a terminal program. To power the board:   Connect the type-B end of a powered USB cable into the receptacle marked X13   or   Supply 5v to the DC connector labeled X14 LPC18xx_HITEX (LPC1850 Hitex Evaluation Board)  newer A3 design schematic ./BSP/schematics/HITEX_Final_LPC1850EVA-A3.pdf PC configuration Use a PC running Windows XP, Vista or 7 to display runtime diagnostics that can be viewed with a terminal emulation program like Teraterm or Hyperterm. The baud rate in these programs should be set to 9600. Build and debug the example LPCXpresso IDE In the project explorer window of the IDE right click on the Example_AudioOutputHost project and select Debug As->C/C++ MCU Application In the main window of the IDE click Run->Resume to start running the application Keil uVision 4 IDE In the Batch Build window, select the project targets as described in Compiler Build Configurations and then click Build In the main window of the IDE click Debug->Start/Stop Debug Session click Debug->Run How this example runs and what to look for When the example is first run the terminal window will display: Audio Output Host Demo running. When the USB speakers are plugged in the terminal window will display: Audio Device Enumerated. When the button is pressed on the board the USB speakers will produce a loud tone. When the button is not pressed the USB speakers will be silent. When the USB speakers are unplugged the terminal window will display: Device Unattached.

This project explains how to build and deploy u-boot for platforms using the LPC177x_8x devices. To build u-boot, you will need to system running the Linux operating system, that latest CodeSourcery GNU tools for the Linux OS, the u-boot source code, and the u-boot patch(es) for the LPC1788. Feaures implemented -------------------------------------------------------------------------------- Support for the EA1788 board with 32-bit DRAM (32MB) Support for the EA1788 board's NAND FLASH Support for the LPC177x_8x internal FLASH Ethernet support Limited MPU support u-boot known issues -------------------------------------------------------------------------------- Issue: 'reset' command causes the board to crash Workaround: Use 'cmreset' command instead Issue: 'boot' command causes the board to crash Workaround: Use environment variables and scripting with go command instead Issue: bootvx command causes board crash Workaround: None, but there is no reason to use this command Feaures not implemented -------------------------------------------------------------------------------- FLASH 'protect' command and features are not implemented (easily implemented) Interrupt/NVIC support not implemented (easily implemented) Possiible improvements -------------------------------------------------------------------------------- Systick can be used instead of the LPC1788 match timer The relocation code has been 'worked around' and is not implemented correctly A macro file for device spcific IRQs ie needed with weak links to be included in the startup file (arch specific with device overrides) A basic MPU driver is there and seems to work, but could be improved The ethernet driver and PHY setup are 'board specific', but could be moved to the drivers area and the generic PHY support could be used u-boot operational bootup overview -------------------------------------------------------------------------------- Here is an overview of how u-boot boots on the LPC1788. - LPC1788 boot ROM transfer control to u-boot code in internal FLASH at address 0x0 per CM3 bootup procedure - u-boot code first sets up the MPU - Pin muxing, clocking, and DRAM are all initialized - Code and data are relocated from FLASH to DRAM - BSS segment is cleared in DRAM - Control is transferred to u-boot code in DRAM - u-boot board_init_f() is called which does initial u-boot setup - board_init_r() is called for later u-boot setup - u-boot operates normally out of DRAM Location of the ported files -------------------------------------------------------------------------------- arch/arm/cpu/cortex-m3 - Cortex M3 specific files (mpu, startup, etc.) arch/arm/cpu/cortex-m3/lpc1788 - LPC1788 specific files (timer, serial, etc.) arch/arm/include/asm/arch-cortex-m3 - Cortex M3 header files arch/arm/include/asm/arch-lpc17xx - LPC177x_8x specific header files board/nxp - board specific area for board using NXP devices board/nxp/ea1788 - EA1788 board specific files (setup, nand, etc.) include/configs/ea1788.h - EA1788 board specific configuration file

Introduction Adding IOH functionality to a custom project is not difficult, but does involve a few important steps. These steps are explained in more detail on this page. Since the implementation of most of the steps are IDE dependant, details for each supported IDE (LPCXpresso, Keil MDK, IAR EWARM) are given on seperate pages.   Steps in general In general, the following steps should be followed when using an IOH library in a custom project: 1. Add the IOH library (*.lib, *.a) to the project. 2. Add the path where the library's header file resides to the project’s include path. 3. #include the IOH header file in the source code of the application. 4. Configure the linker to place the IOH related sections in the IOH SRAM using our provided linker scripts (for LPCXpresso this step is performed automatically when an IOH enabled device is selected). 5. Enable the IOH SRAM (SRAM1) before C-library initialization (startup/system_init code). 6. Interact with IOH via the library's API.   Detailed instructions per IDE For more detailed, per IDE instructions, visit the pages below: LPCXpresso Keil MDK IAR EWARM

Introduction This page gives more detailed information on how to use the IOH libraries in custom projects when using the Keil MDK IDE. For more general information regarding using IOH libraries in custom project or for detailed instructions for LPCXpresso and IAR EWARM, visit IOH: Getting started with IOH in custom projects. Ready-to-use examples can be found at the main I/O Handler page. Note: This guide assumes the IOH I2S library is to be added to a project, hence the 'I2S' references. For other IOH libraries, 'I2S' should be replaced with the library name. 1. Add the IOH library (ioh_*_keil.lib) to the project The first step is to configure the Keil project to link against the IOH library. This can be done by simply adding the .lib file to the project. 2. Add the path where the library's header file resides to the project’s include path The next step is to add the file location of the library's header file to the include path of the project. Open the project options and browse to the tab 'C/C++'. Add the location of the header file to the 'Include Paths'. 3. #include the IOH header file in the source code of the application The IOH header file must be included in the source code of the project (e.g. main.c) by using the following preprocessor directive: #include "IOH_I2S.h" 4. Configure the linker to place the IOH related sections in the IOH SRAM All IOH parts have an SRAM region reserved for I/O Handler. When starting IOH, usually by calling the library's init() function, I/O Handler expects this memory region to be loaded with the IOH data provided by the IOH library. This means this data must be stored in Flash and copied to the IOH SRAM upon startup. A convenient way to do this, is by using scatter loading. With scatter loading, the linker and c-library are instructed to program certain data sections (IOH data) into Flash, and copy it to the specifed region (IOH SRAM) upon start up. This requires a linker script. The linker script can be added to the keil project by opening the projects options and browsing to the 'Linker' tab. First uncheck the 'Use memory Layout from Target Dialog' checkbox, then add the file location to the 'Scatter file' box. Following is the linker script used for the LPC11U37H, placing the IOH sections in the SRAM1 region (IOH SRAM): LR_IROM1 0x00000000 0x00020000  {    ; load region size_region   ER_IROM1 0x00000000 0x00020000  {  ; load address = execution address    *.o (RESET, +First)    *(InRoot$$Sections)    .ANY (+RO)       }   RW_IRAM1 0x10000000 0x00002000  {  ; RW data    .ANY (+RW +ZI)   }   RW_IRAM2 0x20004000 0x00000800  {  ; RW data    .ANY (+RW +ZI)   }   RW_IRAM3 0x20000000 0x00000800  {  ; RW data    .ANY(.ioh_text)    .ANY(.ioh_constdata)    .ANY(.ioh_bss)    .ANY(.ioh_data)   } } 5. Enable the IOH SRAM (SRAM1) before C-library initialization The copying of data from the 'load region' to the 'execution region' when using scatter loading (explained above) is executed by the c-library just before main() gets called. It's important that both regions are enabled when the copying is initiated. After power-on, the IOH SRAM on the LPC11E/U37H is disabled (clock disabled in the SYSAHBCLKCTRL register), so it must be enabled before the scatter loading is initiated. The right place (assuming the CMSIS standard is followed) to enable the IOH SRAM, is in the SystemInit function. SystemInit() is called just before the C-enviroment is initialized as can been seen from the following snippet from the LPC11xx Keil startup file: Reset_Handler   PROC EXPORT  Reset_Handler             [WEAK] IMPORT  SystemInit IMPORT  __main LDR     R0, =SystemInit BLX     R0 LDR     R0, =__main BX      R0 ENDP Therefore the SystemInit() function should contain the code for enabling the IOH SRAM block, e.g. by adding the following line to the SystemInit() function (assuming the LPC11E/U37H): LPC_SYSCON->SYSAHBCLKCTRL |= (1<<26); 6. Interact with IOH via the library's API The final step is to interact from the application with IOH. This can be done through the library's API. Each library comes with an application note explaining how to use the library and what data structures and functions are available, and with one or more application examples showing how to use the library. This application note and application example provide an easy way to get started. They can be downloaded from the main I/O Handler page.

Introduction The LPC4088 based Closed Loop Payment demo shows how a basic closed loop payment system can be created using NXP’s ARM Cortex-M4 based LPC4088.  The leading industry-standard MIFARE contactless and dual interface smart card is used for payment and is fully compliant with ISO 14443A. A 7” 800x480 color touch-screen LCD functions as a graphical user interface (GUI). Using this graphical interface, the card can be queried, items to buy can be selected, and finally the user can proceed to checkout.  The GUI is build using emWin. NXP's CLRC663, a contacless reader IC, is used to interface with the MIFARE card. This demo also features the usage of the SPIFI peripheral. A 32Mbit QSPI FLASH chip is used for storing images used by the demo. Demo Video Links NXP Secure Transaction Website on EETimes LPCWare emWin project page NXP ARM Cortex-M4 Product Page NXP CLEV663B demoboard (Blueboard) Getting started with the RC663 Blueboard Embedded Artists LPC1788 Evaluation Board (LPC4088 OEM module required for this demo) Embedded Artists LPC4088 Developers Kit (Baseboard + LPC4088 OEM module) Embedded Artists 7" 800x480 color LCD Software Encryption Solutions

If you plan on using NAND FLASH for booting your system, the recommendation is to use the MLC NAND controller for initially booting a small 'kickstart' image from block 0, and then using the loaded kickstart image to boot and load a full image from blocks 1 and on using the NAND SLC controller. The kickstart image cannot exceed 56K bytes in size on a large page FLASH device or 15.5K bytes in size on a small page device. A question often asked is "Why isn't the MLC NAND controller just used for everything?". The MLC NAND controller has stronger ECC support, but is limited on data layout. The minimum transfer size when using ECC is 528 bytes. Because of this 528 bytes transfer size, the ECC is also computed on the non-payload data area. Operating systems that use the spare area in NAND FLASH (such as the Linux MTD OOB area) will not be able to actively alter just the spare area without erasing and altering the entire block. This means that items such as bad block markers, JFFS2 clean markers, or block leveling data can't be stored outside the main page data's ECC algorithm. Because of this, the MLC controller can't readily be used for normal data operations.

For small and large page NAND devices, the data is typically organized as follows:   Small page NAND FLASH (factory) Bytes 0 - 511        : Main data payload area Bytes 512 - 515      : Spare data area, 4 bytes Bytes 516 - 517      : Factory bad block marker area (typical) Bytes 518 - 527      : Spare data area, 10 bytes   Large page NAND FLASH (factory) Bytes 0 - 2047       : Main data payload area Bytes 2048 - 2048    : Factory bad block marker area (typical) Bytes 2049 - 2111    : Spare data area, 63 bytes   The LPC32x0 MLC NAND controller uses the following storage approach when used with ECC: Small page NAND FLASH, MLC NAND controller with ECC Bytes 0 - 517        : Main data payload area Bytes 518 - 527      : ECC data area   Large page NAND FLASH, MLC NAND controller with ECC Bytes 0 - 517        : Main data payload area, subpage 1 Bytes 518 - 527      : ECC data area, subpage 1 Bytes 528 - 1045     : Main data payload area, subpage 2 Bytes 1046 - 1055    : ECC data area, subpage 2 Bytes 1056 - 1573    : Main data payload area, subpage 3 Bytes 1574 - 1583    : ECC data area, subpage 3 Bytes 1584 - 2101    : Main data payload area, subpage 4 Bytes 2102 - 2111    : ECC data area, subpage 4   The LPC32x0 SLC NAND controller uses the following storage approach when used with ECC: Small page NAND FLASH, SLC NAND controller with ECC Bytes 0 - 255        : Main data payload area, subpage 1 Bytes 256 - 511      : Main data payload area, subpage 2 Bytes 512 - 515      : Spare data area, bytes 0 - 3 Bytes 516 - 517      : Bad block marker Bytes 518 - 521      : Spare data area, bytes 4 - 7 Bytes 522 - 524      : ECC data area, subpage 1 Bytes 525 - 527      : ECC data area, subpage 2   Large page NAND FLASH, SLC NAND controller with ECC Bytes 0 - 255        : Main data payload area, subpage 1 Bytes 256 - 511      : Main data payload area, subpage 2 Bytes 512 - 767      : Main data payload area, subpage 3 Bytes 768 - 1023     : Main data payload area, subpage 4 Bytes 1024 - 1279    : Main data payload area, subpage 5 Bytes 1280 - 1535    : Main data payload area, subpage 6 Bytes 1536 - 1791    : Main data payload area, subpage 7 Bytes 1792 - 2047    : Main data payload area, subpage 8 Bytes 2048 - 2049    : Bad block marker Bytes 2050 - 2087    : Spare data area, 38 bytes Bytes 2088 - 2090    : ECC data area, subpage 1 Bytes 2091 - 2093    : ECC data area, subpage 2 Bytes 2094 - 2096    : ECC data area, subpage 3 Bytes 2097 - 2099    : ECC data area, subpage 4 Bytes 2100 - 2102    : ECC data area, subpage 5 Bytes 2103 - 2105    : ECC data area, subpage 6 Bytes 2106 - 2108    : ECC data area, subpage 7 Bytes 2109 - 2111    : ECC data area, subpage

Attached is another simple SWIM demo that setups a 240x320 window and draws an animated diamond in the window as fast as possible. Although the code is meant to be used with the LPC32x0 CDL, it can be easily ported to other devices. The code for setting up the window and doing the animations is below: /* Create a SWIM window */ swim_window_open(&win1, LCD_DISPLAY.pixels_per_line,     LCD_DISPLAY.lines_per_panel, fblog1, 0, 0,     (LCD_DISPLAY.pixels_per_line - 1),     (LCD_DISPLAY.lines_per_panel - 1), 3, WHITE, BLACK, MAGENTA);     xf = 20;     yf = 30;     xinc = 1;     yinc = 1;     clr = RED | GREEN;     /* Draw as fast as possible, no throttling */     while (1)     {        swim_set_fill_color(&win1, clr);        swim_put_diamond(&win1, LCD_DISPLAY.pixels_per_line / 2,        LCD_DISPLAY.lines_per_panel / 2, xf, yf);        lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF1);        xf += xinc;        if ((xf < 10) || (xf > 150))            xinc = -xinc;        yf += yinc;        if ((yf < 10) || (yf > 230))            yinc = -yinc;        clr++;        if (clr > 0xFFFF)            clr = RED | GREEN;     } The file also includes a pre-built image of the program for use with the Phytec LPC3250 board using S1L. To use the image, just boot the board to the S1L prompt, type "load term srec', send the SREC file to the board via the serial port (no transfer protocol), and then type 'exec' to start it.