volatile preventing ldrb byte access?

[lpcware]

Content originally posted in LPCWare by cyberstudio on Mon Mar 17 17:58:09 MST 2014
I am using the GPIO "byte access" registers available on some LPC microcontrollers. The LPCOpen library defines those as:

typedef struct {/*!< GPIO_PORT Structure */
__IO uint8_t B[128][32];/*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
......<snip>......
} LPC_GPIO_T;

I would expect the ARM byte access instruction would be used to read the port pin, but the generated code for checking if PIO0_14 pin is zero looked like:

23a0      movsr3, #160; 0xa0
05db      lslsr3, r3, #23
68db      ldrr3, [r3, #12]
021b      lslsr3, r3, #8
0e1b      lsrsr3, r3, #24

The strangest thing is, if I remove "_IO" from the struct definition, which was defined to be "volatile", the code generated becomes:

23a0      movsr3, #160; 0xa0
05db      lslsr3, r3, #23
7b9b      ldrbr3, [r3, #14]
2b00      cmpr3, #0

My optimization flag is -Os. My LPCXpresso verion is 7.0.2. This is confounding, as why would a volatile byte turn into a 32-bit word? From an optimization standpoint, one cmp instruction is clearly cheaper than 2 shift instructions, both in space and in time.

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Tue Mar 18 00:56:18 MST 2014
Try adding the option "-fno-strict-volatile-bitfields" to the compiler options

Project -> Properties -> C/C++ Build -> Settings -> Tool Settings …
… -> MCU C Compiler -> Optimization -> Other optimization flags.

Does this cause the LDRB to be generated instead of the LDR?

Regards,
LPCXpresso Support