nvic_SetPriority

[lpcware]

Content originally posted in LPCWare by mcu_programmer on Fri Sep 17 13:13:35 MST 2010
I would like documentation on cmsis nvic functions such as NVIC_SetPriority

is setting priority as simple as choosing a number between 0 (highest) and 3 (lowest priority)?

such as

NVIC_SetPriority(IRQm, 2);

I've seen this on the net,

NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);

Original Attachment has been moved to: 1100692_log.zip

[lpcware]

Content originally posted in LPCWare by Jesse.Rosenberg on Wed Sep 22 10:35:13 MST 2010
If you are able to post code on the forum I'd be happy to take a look at it and/or pass it along to any relevant members of the NXP team.

[lpcware]

Content originally posted in LPCWare by mcu_programmer on Tue Sep 21 11:57:15 MST 2010
I've been doing some further tests today. Before I was sure it was a timer/interupt issue, however it may not be that.

I'll work on the problem further.

[lpcware]

Content originally posted in LPCWare by mcu_programmer on Tue Sep 21 07:27:58 MST 2010
What I've discovered is that sometimes a timer interupt doesn't get called, sometimes it works (most of the time) when I do a power cycle sometimes it doesn't work, hence I suspect something in the hardware.

I am trying to make a test program that can isolate the problem, however it is a lot of work.

[lpcware]

Content originally posted in LPCWare by mcu_programmer on Tue Sep 21 04:32:28 MST 2010
Hi Jesse,

The *symptoms* is that the interupt doesen't get called. I do not actually believe there is a hardware error in the interupt hardware; after some investigation there is definitaly a hardware error in a peripheral unit.

Please specify an email adress where I can elaborate further details.

[lpcware]

Content originally posted in LPCWare by Jesse.Rosenberg on Mon Sep 20 15:05:59 MST 2010
I am unaware of any interrupt based errata on LPC11xx devices, could you please elaborate as to what you suspect is wrong ?

[lpcware]

Content originally posted in LPCWare by mcu_programmer on Sat Sep 18 04:11:15 MST 2010
Yup.

It is as simple as I thought.

I've discovered LPC111x is hardware buggy when it comes to interupts.

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Fri Sep 17 13:43:55 MST 2010
And the question is :confused:?

You can find __NVIC_PRIO_BITS in your LPCxxxx.h. It declares the number of priority bits of the core (LPC1343=3, LPC1768=5).

So (1 << __NVIC_PRIO_BITS) -1 always defines the highest possible value = lowest possible priority.

Does this answer your question?