lpc1778 adc bust read,channel & result sync problem

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lpc1778 adc bust read,channel & result sync problem

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by novemer on Mon Jan 20 21:57:10 MST 2014
hi all:
i am using the adc function in my project, bust mode. dma enable. mcu is lpc1778fbd144. i read data from ADGDR register. ADINTEN register is set to 0x100(enable the global DONE flg to generate interrupt ONLY). now there is a problem that the data stored by dma is not right. the CHN(bit 26:24 of ADGDR) and RESUALT(bit 15:4 of ADGDR) is not sync. e.g:enable 8 chs to bust read.the first data is 0f ff 00 81.CHN=1,but the data 0xfff is ch0.the second data is 0f ee 00 82.CHN=2,but data 0xeef is ch1...the eighth data is 0f ff 00 80, CHN=0,but the data 0xfff is ch7. other 5 chs are the same proble .that is why?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Wouter on Tue Jan 21 02:26:17 MST 2014
Hi Novemer,

Unfortunately the ADC's global data register cannot be used when using the burst mode, see errata ADC.2: www.nxp.com/documents/errata_sheet/ES_LPC177X_8X.pdf

Regards,
Wouter
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