// <e3> PLL0 Configuration (Main PLL) // <h> PLL0 Configuration Register (PLL0CFG) // <i> F_cco0 = (2 * M * F_in) / N // <i> F_in must be in the range of 32 kHz to 50 MHz // <i> F_cco0 must be in the range of 275 MHz to 550 MHz // <o4.0..14> MSEL: PLL Multiplier Selection // <6-32768><#-1> // <i> M Value // <o4.16..23> NSEL: PLL Divider Selection // <1-256><#-1> // <i> N Value // </h> // </e> |