Where's my stack?

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Where's my stack?

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by skysat on Sat Jan 18 10:34:07 MST 2014
When I am in an interrupt or exception handler (LPC1769), I seem to be missing most of the stack.  The top of the stack is a couple of 0xfffffff8's (what does that mean and where is it documented?).  Yes, for an exception, you can look at VECTPC, but that hardly makes for source code debugging.  In any case, the full stack is required if you want to answer the question, "How did I get here"?  Obviously, the information is available somewhere.  So, is there a button to push (wishful thinking)?  Or, is there a procedure to follow to trick the debugger into showing the rest of the call stacks?

Randy

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by skysat on Mon Jan 20 12:13:30 MST 2014
The following procedure works more generally anywhere in the ISR.  Here is the top of the ISR:

0000bf40:   push    {r7, lr}
0000bf42:   sub     sp, #24
0000bf44:   add     r7, sp, #0

Since you have to modify R7, you have to be in Instruction Stepping Mode and avoid any instruction that uses R7.

Add 0x1C (4 more than the decimal 24 shown above) to R7 and single step.  The stack shows one more entry.  Now subtract x1C from R7 and continue.

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by skysat on Mon Jan 20 11:52:04 MST 2014
Actually, I was able to trick the IDE into displaying the return address (but not the rest of the stack - dang).  Here's how.

248       }
0000c118:   add.w   r7, r7, #24
0000c11c:   mov     sp, r7
0000c11e:   pop     {r7, pc}

This only works if you are already at the last line of the ISR.  In Instruction Stepping Mode, single step past the add.w.  (This actually shows a change to the stack but it is wrong.  On my program, it shows the routine two steps back instead of one.)  Now add 4 to R7 and single-step.  The call stack now shows one more entry on the stack.  This is the return address.  The rest of the stack is still missing.  If you wish to continue, subtract 4 from SP.

Obviously the IDE is a composite of Eclipse and LPCXpresso.  The question is, do you have sufficient control over the stack display to show the full stack.  The information is available somewhere.

Randy

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by lpcxpresso-support on Mon Jan 20 05:08:21 MST 2014
The  0xfffffff8 that you see is actually the 0xfffffff9 (with the bottom bit cleared) that the Cortex-M3 cpu places into the LR register (r14) when it takes an exception. This has a special meaning to the cpu hardware, telling it how to carry out the returned from the handler when it completes.

There is no automated way I can spot of creating a backtrace of where you came from when you stop in an interrupt handler, but you can actually work this out fairly easily.

When you stop in your interrupt handler, look at the address in the SP (r13) register. This gives you a pointer to the stack frame created automatically by the Cortex-M3's interrupt handler entry.

You can then use a memory window to work back through stacked registers to find the address that you will return back to (which is at address of the stack + 0x18), and you can then match this back to your source code - for example by entering the address in the disassembly view (and enabling "Show Source").

One thing you do need to watch for though is that if you set a breakpoint by double clicking in the Source view on an exception handler, this will typically be after initial stacking instructions added by the compiler at the start of the function. Thus you may want to view the disassembly view for the interrupt handler, and set the breakpoint from there. Or else, look at was stacked by the code at the start of the interrupt handler, and offset the appropriate number of extra words.

More information on the stacking of registers on interrupt entry can be found in either the ARMv7M Architecture Reference Manual (ARM ARM):

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html
[registration required]

or in Joseph Yiu's book, "The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors, Third Edition":

http://www.amazon.com/Definitive-Cortex®-M3-Cortex®-M4-Processors-Edition/dp/0124080820/ref=sr_1_1?i...

Regards,
LPCXpresso Support
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