Content originally posted in LPCWare by Muis on Sat Feb 02 16:27:44 MST 2013
Quote: Tsuneo
- IRC (12Mhz) is tuned in +/- 1% in factory. It's enough for RS232 tolerance.
- The timing, in which the system clock switches from IRC to PLL, may be critical, so that it doesn't affect to USART reception. Switch the clock while the RX line is silent, after the first block of data.
I'm already on the IRC (because I assumed its more power efficient than using the external crystal), so I dont need to switch clocks after wake up.
Quote: Tsuneo
- Power consumption in sleep mode may reduce as much as those on deep sleep, when the peripherals, other than USART, aren't fed clock.
I'm really puzzled by this comment, because with all peripherals off I'm still using over 2 mA (at 12Mhz) in normal sleep, while in deep-sleep it should be around 20 μA. I often wondered how it's possible this difference is so large, but its consistent with app-note AN11027 where NXP specifies 6 mA in normal sleep (at 48Mhz) (with all peripherals disabled), and 6 μA in deep-sleep. The reason for this large difference is not clear to me.