WDTOSC for SYS PLL Clock Source

[lpcware]

Content originally posted in LPCWare by ktownsend on Sun Jul 25 23:27:57 MST 2010
In the latest UM for the LPC1343, WDTOSC was removed an an input clock source for PLL.   (P.22 of http://ics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc13xx.pdf)

It's still listed in the main clock src select regsiter (MAINCLKSEL), which is helpful since I'm using this feature for controlled SW wakeup from deep sleep even though it's not terribly accurate (+/-40%).

Was the accuracy the main reason it was removed from SYSPLLCLKSEL?  I'm just curious if there are any implications I should keep in mind using WDTOSC as a clock source for the system in deep sleep, as seen in the code below (see [B]pmuWDTClockInit[/B] and [B]pmuDeepSleep[/B][COLOR=#666600]([/COLOR]uint32_t sleepCtrl[COLOR=#666600],[/COLOR] uint32_t wakeupSeconds)):

http://code.google.com/p/lpc1343codebase/source/browse/trunk/core/pmu/pmu.c

Kevin

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Mon Aug 02 15:31:47 MST 2010
[COLOR=#1f497d][FONT=Calibri]Hello Kevin, [/FONT][/COLOR]
[COLOR=#1f497d][/COLOR]
[COLOR=#1f497d][/COLOR][COLOR=#1f497d][FONT=Calibri]The WDT Osc doesn’t meet the PLL input range. [/FONT][/COLOR]
[COLOR=#1f497d][FONT=Calibri]The WDT Osc is speced from 7.8 kHz to 1.7 MHz.[/FONT][/COLOR]
[COLOR=#1f497d][FONT=Calibri]The PLL input frequency range is from 10 MHz to 25 MHz.[/FONT][/COLOR]

We hope this satisfies your curiosity.