WDT clock settings

[lpcware]

Content originally posted in LPCWare by sallys21 on Tue Mar 12 09:51:55 MST 2013
I'm thoroughly going through my clock setup, since I seem to have issues with always having something wrong and putting my processor in a bad state

Looking at my system_LPC11xx.c file, I noticed that the __WDT_OSC_CLK values don't match what's in the user manual...The __FREQSEL and __DIVSEL seem to be fine to calculate my clock value for the WDT, but the defines for the __WDT_OSC_CLK are different? I'm wondering if that's the reason why my guy keeps resetting and I'm not able to reprogram it?

I have my WDTOSCCTRL_Val = 0x180, so my FREQSEL(Fclkana) = 0xC, and DIVSEL = 0...wdt_osc_clk = 4Mhz/(2*(1+0)) = 2Mhz. But according to my system_LPC11xx.c file, my __WDT_OSC_CLK = 2900000/2 = 1.45Mhz

#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)

#if (CLOCK_SETUP)                         /* Clock Setup              */
  #if (SYSCLK_SETUP)                      /* System Clock Setup       */
    #if (WDTOSC_SETUP)                    /* Watchdog Oscillator Setup*/
        #if  (__FREQSEL ==  0)
          #define __WDT_OSC_CLK        ( 400000 / __DIVSEL)
        #elif (__FREQSEL ==  1)
          #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
        #elif (__FREQSEL ==  2)
          #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
        #elif (__FREQSEL ==  3)
          #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
        #elif (__FREQSEL ==  4)
          #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
        #elif (__FREQSEL ==  5)
          #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
        #elif (__FREQSEL ==  6)
          #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
        #elif (__FREQSEL ==  7)
          #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
        #elif (__FREQSEL ==  8)
          #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
        #elif (__FREQSEL ==  9)
          #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
        #elif (__FREQSEL == 10)
          #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
        #elif (__FREQSEL == 11)
          #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
        #elif (__FREQSEL == 12)
          #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
        #elif (__FREQSEL == 13)
          #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
        #elif (__FREQSEL == 14)
          #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
        #else
          #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
        #endif
    #else
          #define __WDT_OSC_CLK        (1600000 / 2)
    #endif  // WDTOSC_SETUP

[lpcware]

Content originally posted in LPCWare by sallys21 on Tue Mar 12 13:16:46 MST 2013
Okay, I thought you were going to bring something else up. :D

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Tue Mar 12 13:14:16 MST 2013
Datasheet :)

---

Quote:

7.16.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to [COLOR=Red]1 % accuracy[/COLOR] over the entire voltage and temperature range.

---

[lpcware]

Content originally posted in LPCWare by sallys21 on Tue Mar 12 13:10:25 MST 2013
I planned on using the IRC for the clock source of the WDT...is this not accurate either?

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Tue Mar 12 11:31:26 MST 2013
BTW: If you need a more accurate watchdog it's useful to use another timer and measure WDT clock ;)

There's a nice sample which is using this mechanism to time a wakeup (Sample 'timedwakeup' in NXP_LPCXpresso11C24_2011-01-27.zip) :)

[lpcware]

Content originally posted in LPCWare by sallys21 on Tue Mar 12 11:16:06 MST 2013
Aha!

Makes sense.

Thanks Zero :D

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Tue Mar 12 11:02:20 MST 2013
This is obviously a [COLOR=Red]LPC13xx[/COLOR] Fclkana table in CMSISv2p00_LPC11xx :eek::mad::eek:

Probably because no one expects this clock to be accurate (Datasheet: 'The frequency spread over processing and temperature is[COLOR=Red] +- 40 %[/COLOR]') :p