UART usage when "RX Trigger Level!=0"

[lpcware]

Content originally posted in LPCWare by BM10 on Tue Nov 06 13:16:23 MST 2012
Hi all.

I've been trying to find an answer to a question that has been bugging me for quite some time. I am sure that the answer is simple but I am also a newbie, so be patient.

This is the scenario:
I am using a LPC1769 UART port to communicate with a GPS module. So far, I was able to transmit data to the GPS module successfully.
However, on the receiving part, I was not so lucky.
My objective is to build the receiving code that triggers as little UART interruptions as possible.
From what I've seen so far on the User Manual, I can accomplishe this by:
1- Operating the UART port using DMA
or
2- Configuring the "RX Trigger Level" on FCR register to 14 characters

Once this is done I'll be able to do some test and check which option has better performance.


My real problem concerns option "2". How to use the UART with "RX Trigger Level" different from 1 character?


From what I understood, the "RX Trigger Level" "determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated." (UM §14.4.6)


Question1: Considering that the received data is stores in Receiver Buffer Register (wich is only 1 byte long), where are the remaining characters stored when "RX Trigger Level!=0" and the UART interrupt is triggered?

Question2: "§14.2 Features" state that LPC1769 has "16 byte Receive and Transmit FIFOs". Where are they? Which register? How can I use them



I hope I was able to explain my doubts clearly.

Any clarification, tutorial and/or sample code is wellcome (All the sample code I found so far is using "RX Trigger Level==0").
Thanks in advance.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Wed Nov 07 02:12:44 MST 2012
[FONT=Tahoma][SIZE=1]The manual does not state explicitly to read the received character register multiple times, but[/SIZE][/FONT][FONT=Tahoma][SIZE=1] it does say:

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Quote:
[FONT=Tahoma][SIZE=1]The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.[/SIZE][/FONT]

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[FONT=Tahoma][SIZE=1]
I know that the manual is frustrating and ambiguous at times:(, but it is all
we have and, usually, the information is there (or can be inferred) somewhere.

Cheers, Mike

[/SIZE][/FONT]

[lpcware]

Content originally posted in LPCWare by BM10 on Tue Nov 06 17:20:34 MST 2012
This sentence:
"... you can read (and save) the RBR register 14 (or whatever) times, each time it will return the next character from the (hardware) fifo."
clarified any doubt I had.

Perhaps I didn't read the UM with the necessary attention or my English betrayed me (and something got lost in translation), but I don't recall reading that RBR should be read "trigger level" times.

Either way, the doubt I had, vanished.
Thank you very much for the support Mike.
Cordially.

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Tue Nov 06 14:01:07 MST 2012
[FONT=Tahoma][SIZE=1]The fifo registers are not visible to the user.

After setting the trigger level (e.g. to 14), you will get an interrupt after the 14th character has been
received. [Assuming that you enabled the RBRIE bit in the IER register.]

In the interrupt, read the IIR to see what interrupt occured.

If INTID is 2, you can read (and save) the RBR register 14 (or whatever) times, each time it will
return the next character from the (hardware) fifo.

You can also get a CTI interrupts if there is a least 1 character in the fifo (but less than the trigger
level) and 3 to 3.5 character times have passed without reading the fifo.

See the text description after the IIR register in the user manual.

Cheers, Mike

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