System with multiple interrupts

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Dave3891 on Sun Sep 16 10:42:04 MST 2012
I am developing a system with multiple interrupts and I wanted some advice if my basic concept is a good way to do it.

The basic idea is the system reads a script from a sdcard and processes data based on the script, then a 1ms update loop sends either the new data or the same data back to a FPGA via SPI.
My basic system structure would be as follows

Modules:
    SSP0 (Send/Recv from FPGA SPI Module)
    SSP1 (SDCARD Using FatFS)
    SYSTICK (1ms time to send new data)
    UART (Send/Recv from PC)

Interrupt Levels:
    SYSTICK = 0
    SSP0 = 0
    SSP1 = 1
    UART = 1

Main:
    Read data from SDCARD on SSP1
    Process data and calculate frame data
    Set FrameDataRdy flag
    Preform other tasks
    Process UART Data

SYSTICK:
    Check for FrameDataRdy flag
    begin first frame of transfer on SSP0
    Set FrameTransfer flag
    Clear FrameDataRdy flag

SSP0 (transfer complete):
    Check if FrameTransfer is set
    Get next block of data
    Send data and read recieve register
    if last block clear FrameTransfer flag

UART:
    Move data from hardware buffer to 
    large software buffer

Any suggestions on if this is a good way to set this up would be appreciated

Thanks
Dave

lpcware · ‎06-15-2016

Content originally posted in LPCWare by graynomad on Mon Sep 17 17:11:40 MST 2012
On the surface what you propose seems good, I'm sure there'll be a gotcha or two though, there always is :)

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Dave3891 on Mon Sep 17 08:20:41 MST 2012
Are there any other issues that you think I might run in to ?

Thanks
Dave

lpcware · ‎06-15-2016

Content originally posted in LPCWare by graynomad on Mon Sep 17 07:52:27 MST 2012

Quote:
I need the systick to time the transfers to a 1ms interval

OK, that's reasonable.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Dave3891 on Sun Sep 16 18:44:37 MST 2012
I need the systick to time the transfers to a 1ms interval
The FPGA will be controlling a pulse generator and have a 1ms update interval.

I was thinking that the FrameTransfer will only be set when the data is ready, send the frame, get cleared and wait for the next 1ms interrupt.
Maybe I am missing some timing calculations but I think the frame should be sent in much less then 1ms

Dave

lpcware · ‎06-15-2016

Content originally posted in LPCWare by graynomad on Sun Sep 16 18:16:18 MST 2012

Quote:
Set FrameTransfer flag
Clear FrameDataRdy flag
SSP0 (transfer complete):
Check if FrameTransfer is set

I think that FrameTransfer will always be set, the fact that you got the SSP0 interrupt means that a frame is in progress so you don't need the flag.

If you want to prepare multiple frame/packets/whatever in the main code and have the ISR send them if available maybe a counter that is incremented by the main code and tested/decremented by the SSP0 ISR.

Also I don't see the need for the SysTick ISR, it's essentially just starting a transfer and passing a flag to the SSP0 ISR, main() could do that by itself I think.