SSP. How sync rx FIFO to data frame signal?

[lpcware]

Content originally posted in LPCWare by fanzcsc on Tue Aug 14 10:17:16 MST 2012
We're receiving 16-bit data frames into an LPC1313/1343 MCU's SSP unit. The MCU SSP is configured as a slave. Data comes from a peripheral who's clock we don't
control. We also do not signal the start of data sending. If we enable SSP reading at any given time, the first bit received may not be the start of the data frame. We need to fix this alignment issue and ensure that the first byte received in the SSP's FIFO is the start of a data frame.

We do have a signal that can indicate the start of a data frame. We can interrupt on this and immediately clear the FIFO to sync the buffer data with the start of the data frame. However, because data comes in quite fast, I'm concerned that we may not be able to respond in time.  In order to clear the FIFO on a GPIO interrupt, we'd need to respond in 1/2 of the SPI CLK rate or, let's say, ~100 MCU clocks. Our MCU also works as a slave for another serial line that also requires a high priority interrupt.

So... is it possible to configure the SSP's SSEL input in hardware so that an edge indicates a data frame start? It could
- clear the FIFO on an SSEL edge,
or
- prevent filling the FIFO until the next SSEL edge

If this isn't supported in the LPC1313 or 1343, is there another model that has this?


Thanks,

Fan

[lpcware]

Content originally posted in LPCWare by fanzcsc on Thu Aug 16 10:59:21 MST 2012
Yes we could clear FIFO at first.

However, We could not ensure that other side always sends MSB fromstarting point.

We only know another side will assert chip select before sendingMSB.

So we have to clear FIFO buffer only when chip select is assertedto sync MSB.

Another side will assert chip select one sampling clock beforesending MSB. However, I am not sure if this one sampling clock periodof time is long enough for us to do data sync even though samplingfrequency is a lot lower than micro controller frequency.

Is is possible to increase the priority of chip select interruptprocess as high as possible to avoid it being interrupted?


Thanks,

Fan

[lpcware]

Content originally posted in LPCWare by graynomad on Thu Aug 16 01:18:47 MST 2012

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Quote:
We do have a signal that can indicate the start of a data frame. We can  interrupt on this and immediately clear the FIFO to sync the buffer data  with the start of the data frame.

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I'm suggesting is that the FIFO is already cleared before the interrupt.

Your problem seems to be that it takes too long to purge the FIFO, do that first then when the time comes there's nothing much to do.

In fact if the data is < the FIFO depth you don't have to respond at all I think.

[lpcware]

Content originally posted in LPCWare by fanzcsc on Wed Aug 15 10:17:55 MST 2012
Thanks for your suggestion.

However, our micro controller works as SSP slave mode and can not control SSP master's clock.


Best,

Fan

[lpcware]

Content originally posted in LPCWare by graynomad on Wed Aug 15 07:51:47 MST 2012
I don't know if what you ask is possible, but can't you clear and disable the SSP then just enable it when you get the SOF signal?

EDIT:

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Quote:
configure the SSP's SSEL input in hardware so that an edge indicates a data frame start?

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Enable the interrupt on the SS pin?