SPI slave on LPC1343

[lpcware]

Content originally posted in LPCWare by jookie on Mon Apr 22 02:06:47 MST 2013
Hello,

just 2 quick (dumb) questions :)
- 14.7.5 SSP Clock Prescale Register -- 'In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the SSP peripheral clock...' -- does this mean that when my LPC is running on 72 MHz, then maximum clock (SCK) in SPI slave mode can be 6 MHz? (~ 6 Mbit, 0.75 MB/s)

- does the SPI CS line have to toggle (go H and L) for every received byte in SPI slave mode? (found somewhere here, on forum).

Jookie

[lpcware]

Content originally posted in LPCWare by daniel.widyanto on Mon Apr 22 21:11:34 MST 2013
1) Yup. Max SSP in slave mode is (Main Clock / SSPxCLKDIV / 12). Assuming your Main Clock is 72Mhz, SSPxCLKDIV = 1, your max transfer rate is 6Mbit/sec

2) Yup. The SSEL must toggle in between the SPI frame.