SPI Slave LPC1769

[lpcware]

Content originally posted in LPCWare by guillaumeL on Wed Oct 03 11:59:19 MST 2012
Hello,

  I'm developping a SPI slave (using SSP1) on LPC1769 target. The Master ( FPGA) is sending SPI frame (up to 255 bytes by frame). Unfortunately, When the LPC1769 received the frame a RX FIFO full flag occur and I can only read 8 bytes.Is there any possibility to read this 255 bytes frame, or the frame length is limited to 8 bytes?

Regards.

[lpcware]

Content originally posted in LPCWare by guillaumeL on Thu Oct 04 09:54:03 MST 2012
Thanks, it works fine with the DMA.

Regards,

[lpcware]

Content originally posted in LPCWare by daniel.widyanto on Wed Oct 03 21:06:43 MST 2012
Hi,

The SSP1 has 8-frame of FIFO. So if the frame is set to 8-bits / frame, it will hold 8-bytes before the FIFO is full.

To catch the whole 255-bytes with minimum interrupt, you can use the LPC1769's DMA. Just set the DMA to fetch the data from SSP1, deliver it to your program buffer, count / no of bytes 255 and interrupt the MCU when it's done.