Content originally posted in LPCWare by ArriaLive on Tue Oct 15 12:28:08 MST 2013
Again, thanks for everyone's help. Your direction led me to do some testing. Here's what I've learned.
I am running the PLL1 clock at 180MHz to drive the processor at the full rate. That should be fine. However, I was dividing that rate by 2 to drive the SPIFI rate at 90MHz. At first glance, the specs on the Spansion flash memory part say it can read at 104MHz, so 90MHz should be fine, right? Wrong.
104MHz would be true in serial mode, but in Quad mode, which is what the Xplorer board uses, the max clock frequency on the Spansion flash memory is 80MHz.
So, I changed the divider value to 3 to reduce the SPIFI clock rate down to 60MHz, and voila, everything works great. I can boot on power up. Problem solved.
I'm not sure why with the JTAG board attached it actually did work at 90MHz. I can only assume that the JTAG interface somehow slowed the processor just enough that it worked out ok, but without the debug board attached, the flash memory just couldn't keep up. Is that logical?
I hope this information is useful to others!
Thanks,
EdA