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Reset Pullup 11E14

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Reset Pullup 11E14

‎06-15-2016 05:19 PM
1,056件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by OXO on Thu May 16 03:25:38 MST 2013
Hi, I've done a couple of projects with this part now, and haven't had a reset pullup fitted.

The most recent one has odd behaviour with the debugger, and won't connect unless I have a scope probe on the reset line.

Have a I missed a requirement for a pullup? I searched the docs, and no mention.
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‎06-15-2016 05:19 PM
1,035件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by R2D2 on Thu May 16 06:55:14 MST 2013
Quote:

See Figure 12 for the reset pad configuration.
RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. The reset pin includes a fixed 20 ns glitch filter
And Figure 12 shows an internal (weak) pullup.

Quote:

An external pull-up resistor is required on this pin for the Deep power-down mode.
'this pin' is the WAKEUP pin here, not Reset.
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‎06-15-2016 05:19 PM
1,035件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by serge on Thu May 16 06:16:44 MST 2013
As per datasheet
Quote:


[SIZE=1][FONT=Arial][B][SIZE=1][FONT=Arial]RESET — [/FONT][/SIZE][/B]
[LEFT][/FONT][/SIZE][FONT=Arial][SIZE=1][FONT=Arial][SIZE=1]External reset input with 20 ns glitch filter. A[/SIZE][/FONT][/SIZE][/FONT][/LEFT]

[SIZE=1][FONT=Arial][LEFT][SIZE=1][FONT=Arial]LOW-going pulse as short as 50 ns on this pin resets the[/FONT][/SIZE]
[LEFT][SIZE=1][FONT=Arial]device, causing I/O ports and peripherals to take on their[/FONT][/SIZE]
[SIZE=1][FONT=Arial]default states, and processor execution to begin at address[/FONT][/SIZE]
[SIZE=1][FONT=Arial]0. This pin also serves as the debug select input. LOW[/FONT][/SIZE]
[SIZE=1][FONT=Arial]level selects the JTAG boundary scan. HIGH level selects[/FONT][/SIZE]
[SIZE=1][FONT=Arial]the ARM SWD debug mode.[/FONT][/SIZE][/FONT][/SIZE][/LEFT]
[/LEFT]
[SIZE=1][FONT=Arial]
[/FONT][/SIZE]

[LEFT]So if you want to be sure that you enter SWD mode a pull-up resistor is necessary.[/LEFT]

[LEFT]Also if you want to use deep sleep then a pull-up is mandatory.[/LEFT]
Quote:


[FONT=Arial][COLOR=#005042][LEFT][B][FONT=Arial][COLOR=#005042]RESET pin (pin RESET_PIO0_0)[/COLOR][/FONT][/B]
[LEFT][/COLOR][/FONT][FONT=Arial][SIZE=2][FONT=Arial][SIZE=2]See[/SIZE][/FONT][/SIZE][/FONT][FONT=Arial][SIZE=2] [/LEFT]

[/SIZE][/FONT][FONT=Arial][SIZE=2][COLOR=#0000ff][FONT=Arial][SIZE=2][COLOR=#0000ff][FONT=Arial][SIZE=2][COLOR=#0000ff]Figure 12 [/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][FONT=Arial][SIZE=2][FONT=Arial][SIZE=2]for the reset pad configuration. RESET functionality is not available in[/SIZE][/FONT][/SIZE][/FONT][/LEFT]

[SIZE=2][FONT=Arial][LEFT][SIZE=2][FONT=Arial]Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep[/FONT][/SIZE]
[LEFT][SIZE=2][FONT=Arial]power-down mode. An external pull-up resistor is required on this pin for the Deep [/FONT][/SIZE][SIZE=2][FONT=Arial]power-down mode. The reset pin includes a fixed 20 ns glitch filter.[/FONT][/SIZE][/FONT][/SIZE][/LEFT]
[/LEFT]
[SIZE=2][FONT=Arial]
[/FONT][/SIZE]
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‎06-15-2016 05:19 PM
1,035件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by R2D2 on Thu May 16 04:04:35 MST 2013
Quote: OXO
Have a I missed a requirement for a pullup? I searched the docs, and no mention.


Really? See #2 of http://knowledgebase.nxp.com/showthread.php?p=4643
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