ヘルプ
英语（美国） | English (US) 日本語 | Japanese 中文 | Chinese (Simplified)

Reset Pullup 11E14

キャンセル
提案をオンにする
自動提案では、入力時に可能な一致が提案されるので検索結果を素早く絞り込むことができます。
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Reset Pullup 11E14

‎06-15-2016 05:19 PM
1,057件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by OXO on Thu May 16 03:25:38 MST 2013
Hi, I've done a couple of projects with this part now, and haven't had a reset pullup fitted.

The most recent one has odd behaviour with the debugger, and won't connect unless I have a scope probe on the reset line.

Have a I missed a requirement for a pullup? I searched the docs, and no mention.
0 件の賞賛
返信
3 返答（返信）

‎06-15-2016 05:19 PM
1,036件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by R2D2 on Thu May 16 06:55:14 MST 2013
Quote:

See Figure 12 for the reset pad configuration.
RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. The reset pin includes a fixed 20 ns glitch filter
And Figure 12 shows an internal (weak) pullup.

Quote:

An external pull-up resistor is required on this pin for the Deep power-down mode.
'this pin' is the WAKEUP pin here, not Reset.
0 件の賞賛
返信

‎06-15-2016 05:19 PM
1,036件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by serge on Thu May 16 06:16:44 MST 2013
As per datasheet
Quote:


[SIZE=1][FONT=Arial][B][SIZE=1][FONT=Arial]RESET — [/FONT][/SIZE][/B]
[LEFT][/FONT][/SIZE][FONT=Arial][SIZE=1][FONT=Arial][SIZE=1]External reset input with 20 ns glitch filter. A[/SIZE][/FONT][/SIZE][/FONT][/LEFT]

[SIZE=1][FONT=Arial][LEFT][SIZE=1][FONT=Arial]LOW-going pulse as short as 50 ns on this pin resets the[/FONT][/SIZE]
[LEFT][SIZE=1][FONT=Arial]device, causing I/O ports and peripherals to take on their[/FONT][/SIZE]
[SIZE=1][FONT=Arial]default states, and processor execution to begin at address[/FONT][/SIZE]
[SIZE=1][FONT=Arial]0. This pin also serves as the debug select input. LOW[/FONT][/SIZE]
[SIZE=1][FONT=Arial]level selects the JTAG boundary scan. HIGH level selects[/FONT][/SIZE]
[SIZE=1][FONT=Arial]the ARM SWD debug mode.[/FONT][/SIZE][/FONT][/SIZE][/LEFT]
[/LEFT]
[SIZE=1][FONT=Arial]
[/FONT][/SIZE]

[LEFT]So if you want to be sure that you enter SWD mode a pull-up resistor is necessary.[/LEFT]

[LEFT]Also if you want to use deep sleep then a pull-up is mandatory.[/LEFT]
Quote:


[FONT=Arial][COLOR=#005042][LEFT][B][FONT=Arial][COLOR=#005042]RESET pin (pin RESET_PIO0_0)[/COLOR][/FONT][/B]
[LEFT][/COLOR][/FONT][FONT=Arial][SIZE=2][FONT=Arial][SIZE=2]See[/SIZE][/FONT][/SIZE][/FONT][FONT=Arial][SIZE=2] [/LEFT]

[/SIZE][/FONT][FONT=Arial][SIZE=2][COLOR=#0000ff][FONT=Arial][SIZE=2][COLOR=#0000ff][FONT=Arial][SIZE=2][COLOR=#0000ff]Figure 12 [/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][FONT=Arial][SIZE=2][FONT=Arial][SIZE=2]for the reset pad configuration. RESET functionality is not available in[/SIZE][/FONT][/SIZE][/FONT][/LEFT]

[SIZE=2][FONT=Arial][LEFT][SIZE=2][FONT=Arial]Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep[/FONT][/SIZE]
[LEFT][SIZE=2][FONT=Arial]power-down mode. An external pull-up resistor is required on this pin for the Deep [/FONT][/SIZE][SIZE=2][FONT=Arial]power-down mode. The reset pin includes a fixed 20 ns glitch filter.[/FONT][/SIZE][/FONT][/SIZE][/LEFT]
[/LEFT]
[SIZE=2][FONT=Arial]
[/FONT][/SIZE]
0 件の賞賛
返信

‎06-15-2016 05:19 PM
1,036件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by R2D2 on Thu May 16 04:04:35 MST 2013
Quote: OXO
Have a I missed a requirement for a pullup? I searched the docs, and no mention.


Really? See #2 of http://knowledgebase.nxp.com/showthread.php?p=4643
0 件の賞賛
返信