Pull-up voltage unexpectedly low

lpcware · ‎06-15-2016

Content originally posted in LPCWare by dpalchak on Thu May 06 10:41:00 MST 2010
At what voltage should an unconnected GPIO pin be when the pin is configured as an input with internal pull-ups enabled? On my lpcxpresso board, I consistently measure this voltage to be about 2.3V. This is with the pins in their default mode (as following a reset) and simply floating in air. I have measured with both the processor held in reset and with the processor in an infinite loop and found the same results. In all my tests, Vdd_IO measured about 3.2V.

Why do the internal pull-ups not pull the pins up to Vdd_IO? Has anyone else noticed this behavior? Is this atypical voltage documented somewhere?

David

lpcware · ‎06-15-2016

Content originally posted in LPCWare by cyberstudio on Sun Aug 29 05:12:58 MST 2010
If we route a peripheral to an output pin and do not wish to bit-bang it, PINMODE_OD would become necessary. I doubt if that register increases costs that much relative to its usefulness.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by rcazalis on Wed Aug 25 14:20:17 MST 2010
I've done a soft I2C once on a micro with no OD feature:
If you want pin to be grounded set it as an output and low.
If you want it open set it as an input.

There is a catch on some micro but not on an ARM.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by cyberstudio on Wed Aug 25 12:51:38 MST 2010
Indeed, I am very much disappointed by that, after reading the User Manual. The exceptions are the SCL and SDA pins for I2C, which are in fact open drain, as required by the I2C specifications.

Being able to configure an output pin as open drain is such a basic feature that I fail to understand why it is left out, but LPC11xx and LPC13xx does not have any PINMODE_OD registers.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by renan on Wed Aug 25 09:42:34 MST 2010
Didn't know that!

Renan

lpcware · ‎06-15-2016

Content originally posted in LPCWare by cyberstudio on Wed Aug 25 09:35:37 MST 2010
Thanks! Available in LPC17xx only, not LPC13xx or LPC11xx :(

lpcware · ‎06-15-2016

Content originally posted in LPCWare by renan on Wed Aug 25 04:12:39 MST 2010

Quote:

Is there something like an "open-drain" mode

LPC_PINCON->PINMODE_OD

but I'm not sure how it acts....

Renan

lpcware · ‎06-15-2016

Content originally posted in LPCWare by cyberstudio on Tue Aug 24 23:06:50 MST 2010
What is the pull-down resistance when I switch on the pull-down resistor?

Is there something like an "open-drain" mode where it would pull an output pin to ground for a '0' but leave the pin in high impedance state for a '1'?

lpcware · ‎06-15-2016

Content originally posted in LPCWare by dpalchak on Thu Jul 01 17:32:38 MST 2010

Quote: dpalchak
At what voltage should an unconnected GPIO pin be when the pin is configured as an input with internal pull-ups enabled? On my lpcxpresso board, I consistently measure this voltage to be about 2.3V. This is with the pins in their default mode (as following a reset) and simply floating in air. I have measured with both the processor held in reset and with the processor in an infinite loop and found the same results. In all my tests, Vdd_IO measured about 3.2V.

Why do the internal pull-ups not pull the pins up to Vdd_IO? Has anyone else noticed this behavior? Is this atypical voltage documented somewhere?

David

I just heard back from NXP directly on this issue. According to NXP, the internal pull-up is provided by a FET configured as a current source. As a result, the maximum pull-up voltage will be around 0.7V less than Vdd_IO. The GPIO are designed this way to provide 5V tolerance.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by dpalchak on Tue May 25 11:36:26 MST 2010

Quote: raimond
Sorry that you have problems. I'm not relying on internal pull-ups on my designs, having external pull-ups all the way. By the way, the LPCs are the first micros that I used that have internal pull-ups active at reset. All other micros that I used didn't have this...

I think that NXP should document this strange behaviour...

Yeah, I've updated the design to add external pull-ups for all of the signals where it matters. It's a bit annoying that the internal pull-ups are too weak to work as proper pull-ups, but are strong enough to interfere if you need a signal pulled low by default. You end up having to use a much stronger pull-down, which then just becomes another source of wasted power during normal operation.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by raimond on Tue May 25 11:08:45 MST 2010

Quote: dpalchak
It does cause problems when the microcontroller is connected to other hardware that may have slightly different logic thresholds. For example, many digital ICs have a logic-high input threshold of 0.7*Vcc. For a 3.3V circuit, this threshold is 2.31V. So, if the internal pull-ups only reach 2.3V, the state of the signal as seen by the other IC cannot be guaranteed.

This problem is more than theoretical. I currently have a medical device design using the LPC1313 where I am seeing SPI bus contention as a result of this low pull-up voltage on several chip-select lines.

Sorry that you have problems. I'm not relying on internal pull-ups on my designs, having external pull-ups all the way. By the way, the LPCs are the first micros that I used that have internal pull-ups active at reset. All other micros that I used didn't have this...

I think that NXP should document this strange behaviour...

lpcware · ‎06-15-2016

Content originally posted in LPCWare by dpalchak on Tue May 18 10:23:33 MST 2010

Quote: raimond
I saw this voltage too, didn't paying much attention to it (I thought it was 2.5V). I don't know if it's documented. I think that it is good as it is, I don't see any problems.

It does cause problems when the microcontroller is connected to other hardware that may have slightly different logic thresholds. For example, many digital ICs have a logic-high input threshold of 0.7*Vcc. For a 3.3V circuit, this threshold is 2.31V. So, if the internal pull-ups only reach 2.3V, the state of the signal as seen by the other IC cannot be guaranteed.

This problem is more than theoretical. I currently have a medical device design using the LPC1313 where I am seeing SPI bus contention as a result of this low pull-up voltage on several chip-select lines.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by dpalchak on Tue May 18 10:13:00 MST 2010

Quote: NXP_USA
Are you measuring P0.7? That pin drives the LED. The pullup current is not enough to pull it up all the way to VDD. Another possibility is that you have the LPCXpresso board on the EA baseboard. There are many peripherals on the EA baseboard and depending on which pin you are measuring it could be loaded by one of them, so try removing the LPCXpresso from the baseboard. Unconnected pins with the pullups enabled should read very close to VDD which is about 3.2V on the LPCXpresso board. Finally you did not mention how you are measuring the voltage- most voltmeters are 1M or 10M ohm impedance, but some scopes have 50 ohm inputs which would pull the voltage down.

As I mentioned in my original post, I am measuring the unconnected pin voltage. The LPCXpresso is not connected to any additional hardware. Also, I have measured the same low voltage on each unconnected pin. You mention P0.7, which is not an unconnected pin. I did not measure this voltage.

All of my voltage measurements have been taken using a Fluke-189 DMM.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by NXP_USA on Tue May 11 14:34:20 MST 2010

Quote: dpalchak
At what voltage should an unconnected GPIO pin be when the pin is configured as an input with internal pull-ups enabled? On my lpcxpresso board, I consistently measure this voltage to be about 2.3V. This is with the pins in their default mode (as following a reset) and simply floating in air. I have measured with both the processor held in reset and with the processor in an infinite loop and found the same results. In all my tests, Vdd_IO measured about 3.2V.

Why do the internal pull-ups not pull the pins up to Vdd_IO? Has anyone else noticed this behavior? Is this atypical voltage documented somewhere?

David

Are you measuring P0.7? That pin drives the LED. The pullup current is not enough to pull it up all the way to VDD. Another possibility is that you have the LPCXpresso board on the EA baseboard. There are many peripherals on the EA baseboard and depending on which pin you are measuring it could be loaded by one of them, so try removing the LPCXpresso from the baseboard. Unconnected pins with the pullups enabled should read very close to VDD which is about 3.2V on the LPCXpresso board. Finally you did not mention how you are measuring the voltage- most voltmeters are 1M or 10M ohm impedance, but some scopes have 50 ohm inputs which would pull the voltage down.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by raimond on Fri May 07 09:21:15 MST 2010
I saw this voltage too, didn't paying much attention to it (I thought it was 2.5V). I don't know if it's documented. I think that it is good as it is, I don't see any problems.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by dpalchak on Thu May 06 12:42:01 MST 2010
It doesn't matter how large the pull-up resistance is if nothing is drawing current from the pin. Even if the pull-ups were 100kOhm, for your explanation to be correct the DMM would have to draw 10uA while measuring. This is several orders of magnitude too large.

No, even with 100kOhm pull-up an unconnected pin should read very close to Vdd_IO.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Luis Digital on Thu May 06 11:27:46 MST 2010
Hello,

The answer to your question is:
Because there is a resistance that is several thousand ohms.