PWM1LER register question

[lpcware]

Content originally posted in LPCWare by sjohnson on Wed Jul 06 15:12:57 MST 2011
In the LPC17XX.pdf user manual section 24.6.7 it says "The altered values will become effective at the next reset of the timer (when a PWM
Match 0 event occurs)."

Does it happen when the timer resets or when a Match 0 even occurs, you can reset the timer not on a Match 0 event correct?

thank you
Sheldon

[lpcware]

Content originally posted in LPCWare by sjohnson on Thu Jul 07 13:03:51 MST 2011
Thank you, that's what i was missing. Appreciate the help from both of you

[lpcware]

Content originally posted in LPCWare by Rob65 on Thu Jul 07 07:55:42 MST 2011
Yes!

and I thought I was going mad :p

The content of the match registers is latched into the shadow registers on a reset of the counter.

But ... There is a bit in the PWM Timer Control Register called "PWM Enable".
That name is absolutely misleading!!!
PWM is also enabled when this bit is 0 but, as stated in the UM (section 24.6.2):

---

Quote:
PWM mode is enabled (counter resets to 1). PWM mode causes the shadow
registers to operate in connection with the Match registers. A program write to a
Match register will [COLOR=Red][B]not have an effect[/B][/COLOR] on the Match result [B][COLOR=Red]until the corresponding bit
in PWMLER has been set[/COLOR][/B], followed by the occurrence of a PWM Match 0 event.
Note that the PWM Match register that determines the PWM rate (PWM Match
Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a
Match event will not occur to cause shadow register contents to become effective.

---

Thinking of this strange behaviour I discovered why this is being done:
When you set new values for multiple MRx registers, you then write ones in the PWMLER and then all values are changed simultaneously changed at the next MR0 match event.

If, like me, you are just using the PWM to control things like LEDs you can just leave the PWM_EN bit set to 0. In that case there is no need to write ones into the PWMLER register, now the value of the MRx register is taken over at the next reset of the counter.

So the complete answer is (correct me if I am wrong):

[LIST=1]
[*]When PWM_EN = 0, the altered values become effective when the counter reaches 0
[*]When PWM_EN = 1, the altered values become effective only when the PWMLER bits aer set [I]and[/I] a PWM MR0 match event occurs
[/LIST]
This again shows how carefull you have to be when reading, and interpreting, the UM - even I make mistakes :D

Rob

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Thu Jul 07 07:06:01 MST 2011
A lot of examples use Match 0 to set the cycle time and Match 0 interrupt to reset PWM timer:

/******************************************************************************
** Function name:        PWM_Init
**
** Descriptions:        PWM initialization, setup all GPIOs to PWM0~6,
**                        reset counter, all latches are enabled, interrupt
**                        on PWMMR0, install PWM interrupt to the VIC table.
**
** parameters:            ChannelNum, Duty cycle
** Returned value:        true or false, if VIC table is full, return false
** 
******************************************************************************/
uint32_t PWM_Init( uint32_t ChannelNum, uint32_t cycle )
{
  if ( ChannelNum == 1 )
  {
    match_counter1 = 0;
    LPC_PINCON->PINSEL4 = 0x00001555;    /* set GPIOs for all PWM pins on PWM */

    LPC_PWM1->TCR = TCR_RESET;    /* Counter Reset */ 
    LPC_PWM1->PR = 0x00;        /* count frequency:Fpclk */
    LPC_PWM1->MCR = [COLOR=Red]PWMMR0I;    /* interrupt on PWMMR0, reset[/COLOR] on PWMMR0, reset TC if PWM matches */                
    LPC_PWM1->MR0 = cycle;        /* set PWM cycle */
    LPC_PWM1->MR1 = cycle * 5/6;
    LPC_PWM1->MR2 = cycle * 2/3;
    LPC_PWM1->MR3 = cycle * 1/2;
    LPC_PWM1->MR4 = cycle * 1/3;
    LPC_PWM1->MR5 = cycle * 1/6;
    LPC_PWM1->MR6 = 0;    

    /* all PWM latch enabled */
    LPC_PWM1->LER = LER0_EN | LER1_EN | LER2_EN | LER3_EN | LER4_EN | LER5_EN | LER6_EN;
  }
  else
  {
    return (0);        /* Unknown channel number */
  }

  NVIC_EnableIRQ(PWM1_IRQn);
  return (1);
}

In order to prevent (running) PWM from getting confused, values are changed after timer[COLOR=Red] reset[/COLOR].
Timer reset is done in this example by MR0 (but can of course also done by other match registers). 

/******************************************************************************
** Function name:        PWM_Set
**
** Descriptions:        PWM cycle setup
**
** parameters:            Channel number, PWM cycle, and offset
** Returned value:        None
** 
******************************************************************************/
void PWM_Set( uint32_t ChannelNum, uint32_t cycle, uint32_t offset )
{            
  if ( ChannelNum == 1 )
  {
    LPC_PWM1->MR0 = cycle;        /* set PWM cycle */
    LPC_PWM1->MR1 = cycle * 5/6 + offset;
    LPC_PWM1->MR2 = cycle * 2/3 + offset;
    LPC_PWM1->MR3 = cycle * 1/2 + offset;
    LPC_PWM1->MR4 = cycle * 1/3 + offset;
    LPC_PWM1->MR5 = cycle * 1/6 + offset;
    LPC_PWM1->MR6 = offset;

    /* The LER will be cleared when the Match 0 takes place, in order to
    load and execute the new value of match registers, all the PWMLERs need to
    reloaded. all PWM latch enabled */
    LPC_PWM1->LER = LER0_EN | LER1_EN | LER2_EN | LER3_EN | LER4_EN | LER5_EN | LER6_EN;
  }
  return;
}

[lpcware]

Content originally posted in LPCWare by sjohnson on Thu Jul 07 06:25:42 MST 2011
thank you for the quick reply.

But for clarification, the only way to pull the new values in is to have the Match 0 do the reset? Not just have a match0 event occur?

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Wed Jul 06 16:11:32 MST 2011

---

Quote:

Does it happen when the timer resets or when a Match 0 even occurs, you can reset the timer not on a Match 0 event correct?

---

User manual:

---

Quote:

When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode)

---

PWM example:

LPC_PWM1->MCR = PWMMR0I; /* interrupt on PWMMR0, reset on PWMMR0, reset TC if PWM matches */  

So the answer is: When your Match 0 event resets your timer

Note: we are talking here about 'currently running' PWM.
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