LPC11xx Cortex-M0 Peripherals

[lpcware]

Content originally posted in LPCWare by ArtjomGromak on Tue Mar 20 11:26:12 MST 2012
Hi!
One question about debugging: in Peripherals NVIC regirters view (Memory NVIC selected) from address 0xE000ED08 placed register VECT_OFFSET.
It is error?
If not,  where description of this register?

Thaks.

[lpcware]

Content originally posted in LPCWare by CodeRedSupport on Fri Mar 23 15:51:43 MST 2012
The VTOR register is typically seen as not existing on Cortex-M0. However the ARM v6M Architecture Reference Manual says the following....

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Quote:
Vector Table Offset Register (VTOR)
The vector table base address is fixed at 0x00000000. This register (address 0xE000ED08) is RAZ/WI for ARMv6-M.

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[RAZ/WI = Read as zero, ignore writes].

You can find links to ARM's processor documentation here:

http://support.code-red-tech.com/CodeRedWiki/ArmCpuInfo

Regards,
CodeRedSupport