LPC111x - relocatable vector table ??

[lpcware]

Content originally posted in LPCWare by Fraggle on Wed Mar 24 07:52:37 MST 2010
Dear all!

Both, the LPC111x datasheet and the user manual claim the vector table to be relocatable.  But there seems to be no VTOR at all.

Is this an errata in the documentation or am I missing something here?

Thanks
Dirk

[lpcware]

Content originally posted in LPCWare by NXP_USA on Wed Mar 24 16:42:09 MST 2010
As has been mentioned in several replies, it is possible to relocate the vector table on the LPC11xx. This can be achieved by using the MAP bits of the SYSMEMREMAP register.

It is worth noting that this remapping places the vector table into a fixed location. Unlike Cortex-M3 based devices there is no way to change this location using the vector table offset register.

[lpcware]

Content originally posted in LPCWare by CodeRedSupport on Wed Mar 24 15:06:19 MST 2010
You can download the Architecture Reference manuals for both v6M (for LPC11) and v7M (for LPC13/17) from ARM's website, though this does require a registration:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka11237.html

I would also recommend the Technical Reference Manuals for Cortex-M0 (for LPC11) and Cortex-M3 (for LPC13/17), which can be downloaded, without need to register, from:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka11237.html

With regards to the SYSMEMREMAP register, my reading of this is that, although less flexible than the VTOR mechanism on Cortex-M3, it should allow you to change the actual memory type that the Cortex-M0 will access when it reads from address 0x0. Thus it should be possible to use this register to change the vector table, as you suggest, to be read from the start of RAM rather than the start of FLASH. Note however that I haven't personally tried doing this! 

Regards,

CodeRedSupport

[lpcware]

Content originally posted in LPCWare by brucesegal on Wed Mar 24 12:37:17 MST 2010
Is it possible to get a pdf of the ARMV6M Technical Reference? Seems it is unavailable for download on the ARM site.

Makes it harder to program when the LPC111x user guide is missing information and we can't get the technical reference to fill in some blanks.

Does the SYSMEMREMAP register work as documented on page 13 of the user guide?  If so then the interrupt vectors can be remapped to the beginning of User ram. Which is here  I think ..0x1000 0000 

Something else to try.

Bruce

[lpcware]

Content originally posted in LPCWare by CodeRedSupport on Wed Mar 24 08:46:42 MST 2010
This sounds like a mistake in the LPC11 documentation.

The LPC11 family contains a Cortex-M0 processor core, which implements ARM Architecture v6M. The ARM v6M Architecture Reference Manual (ARM DDI 0419B) states the following....
[INDENT][I][B]Vector Table Offset Register (VTOR)[/B]
The vector table base address is fixed at 0x00000000. This register (address 0xE000ED08) is RAZ/WI for ARMv6-M.[/I]
[/INDENT][RAZ/WI  = Read As Zero, Writes Ignored]

Regards,

CodeRedSupport