LPC1114 - why LED ON when set dir as output ?

[lpcware]

Content originally posted in LPCWare by Nodame on Wed Jan 20 18:04:44 MST 2010
I have a question about PIO0_7 bit of LPCXPresso LPC1114.
PIO0_7 is set to ‘0’ after RESET by the user manual.
Would someone please let me know why LED on the board is ON when set DIR to output ?
(please see the schematics, page 5/5)
------------------------------------------------
The experiment was performed as follows.
(1)
>   LPC_GPIO0->DATA &= 0xF7F;           // Clear PIO0_7 bit
>   LPC_GPIO0->DIR  |= 0x080;           // Configure PIO0_7 as output
>   LPC_GPIO0->DATA &= 0xF7F;           // Clear PIO0_7 bit
 LED is OFF at this moment.
>   LPC_GPIO0->DIR  &= 0xF7F;           // Configure PIO0_7 as input
>   LPC_GPIO0->DIR  |= 0x080;           // Configure PIO0_7 as output
 LED is ON at this moment.  WHY ?
(2)
>   LPC_GPIO0->DIR |= 0x080;            // Configure PIO0_7 as output
 LED is ON at this moment.  WHY ?
>   LPC_GPIO0->MASKED_ACCESS[1<<7] = 0; // Clear PIO0_7 bit
&#61664; LED is OFF at this moment.
------------------------------------------------------------------

[lpcware]

Content originally posted in LPCWare by dphillps on Mon Apr 19 10:03:46 MST 2010
/* After rest, the led is on, but dim */
LPC_IOCON->PIO0_7 |= 0x08;     /* pull-down                */
/* LED is still on, but dim  */
/* I expected it to be off */
/* Do I have defective hardware? */

GPIOSetDir( LED_PORT, LED_RED_BIT, OUTPUT );
/* LED is on (bright) */
GPIOSetValue(LED_PORT,LED_RED_BIT,LED_OFF
/* LED is OFF */

[lpcware]

Content originally posted in LPCWare by NXP_USA on Thu Feb 11 13:02:33 MST 2010

---

Quote: noritan_org
NXP_USA,

OK, let me try to explain about

"initial value of the GPIOnDATA register cannot be recognized by the user."

...

In both cases, the user cannot recognize the reset value of the GPIOnDATA register and the description "reset value" for GPIOnDATA gives no information for users.

---

Hi Noritan_org,

-You are correct. We are removing the initial value of 0 from the user's manuals for the GPIOxDATA registers for the current LPC1xxx family members.

One correction to a previous statement- voltages much above Vdd applied to a pin set as output will result in a current into the pin. Still 3.3V pin output to 5V translation is possible with a pullup... but the pin will have to be controlled using both GPIOxDIR and GPIOxDATA.

Specifics on the I/O pin analog behavior with different voltages and in different modes can be found in the ibis models at:
ics.nxp.com/support/ibis

[lpcware]

Content originally posted in LPCWare by noritan_org on Wed Feb 10 05:29:02 MST 2010
NXP_USA,

OK, let me try to explain about

"initial value of the GPIOnDATA register cannot be recognized by the user."

All of the GPIO pins are configured as INPUT on RESET.  This means the GPIOnDATA register returns the corresponding pin's status as an INPUT. So, the actual value of GPIOnDATA is undetermined on RESET.
When any bits of GPIOnDIR register are set, the corresponding GPIOnDATA register bits are immediately overwritten by the pin's status and GPIOnDATA register returns the overwritten value instead of a reset value.

In both cases, the user cannot recognize the reset value of the GPIOnDATA register and the description "reset value" for GPIOnDATA gives no information for users.

[lpcware]

Content originally posted in LPCWare by NXP_USA on Tue Feb 09 10:27:33 MST 2010

---

Quote: noritan_org
NXP_USA and Rob65,

Thank you for your suggestions.  I understand the specification that the initial output port state depends on the state of the input port when DIR bit is set.

I hope the behavior of the GPIO is described in the user manual when DIR bit is set.  In addition a note is expected to describe the initial value of the GPIOnDATA register cannot be recognized by the user.

And I hope that the VIH/VIL value in the data sheet would be corrected in next revision.

Thanks in advance.

---

Hi noritan_org,

The user manual has been updated internally to describe the pin behavior upon switching to output and the next web release will show the changes. VIH/VIL will also be updated. I am not certain what you mean by the "initial value of the GPIOnDATA register cannot be recognized by the user." The register can be read at any time to determine its value.

-NXP

[lpcware]

Content originally posted in LPCWare by noritan_org on Tue Feb 09 01:34:42 MST 2010
NXP_USA and Rob65,

Thank you for your suggestions.  I understand the specification that the initial output port state depends on the state of the input port when DIR bit is set.

I hope the behavior of the GPIO is described in the user manual when DIR bit is set.  In addition a note is expected to describe the initial value of the GPIOnDATA register cannot be recognized by the user.

And I hope that the VIH/VIL value in the data sheet would be corrected in next revision.

Thanks in advance.

[lpcware]

Content originally posted in LPCWare by Rob65 on Sun Feb 07 03:24:45 MST 2010

---

Quote: NXP_USA

You are right the behavior (output mode initial state reflects the input logic level) is not exactly what one would expect from open-drain port pins. However, although the port pins don't have an open-drain mode the same functionally can generally be implemented without external components.

---

[LIST=1]
[*]Set pin as input with pull up (MODE = 10) - pin is pulled high by the pull up resistor.
[*]Configure pin as pull down (MODE = 01) and then set pin as output and low level - pin is actively pulled down
[*]Configure pin as pull up (MODE = 10) and set as input - pin is pulled high again by pull up resistor
[/LIST]
Yes, this does for a very short time show a pull-down situation on the pin instead of an active pull down and yes - this may even (depending of external hardware) very shortly act as an active high.

It's not a perfect situation and may not work depending of your application.
Instead of setting the pin in internal pull-up mode you can also set it to inactive (MODE = 00) if you use an external pul up.
If pins can also be in a not-driven state (i.e. no external pull up/down) you could put it in repeater mode (11) - floating input pins may influence power consumption.

Rob

[lpcware]

Content originally posted in LPCWare by NXP_USA on Fri Feb 05 11:14:36 MST 2010

---

Quote: noritan_org
I don't think the input threshold of the standard port pins and PIO0_7 pin is not 1/2 VDD.  LPC111x datasheet Rev.00.13 says VIH(min)=2.0V and VIL(max)=0.8V for all voltage supply conditions in the page 30 and 31.  They are defined as 5.0V tolerant input pins with TTL level threshold.

---

We are going to update the datasheet. It should be something more along the lines of 0.3*Vdd and 0.7*Vdd rather than the fixed voltage listed now.

---

Quote: noritan_org

What I am expecting to an open-drain output port is to have only two kind of states, drive LOW and Hi-Z. I don't expect the port drives HIGH even if the driving period is very short like an glitch.

Please imagine standard I2C type of BUS. Do you expect a device driving the BUS as HIGH strongly ?

---

For the case of I2C- the I2C module has an open-drain output and it does not glitch. If a decision was made not to use the I2C module and an I/O pin was bit-banged as I2C then 3.3V glitches could be seen if the I2C bus was running at lower voltages (2.5V). This would not impact the bus because the glitches would only occur if the bus was already in a high state (2.5V or 3.3V). Clock stretching and other I2C features (where the bus is already low) would not be affected because the pin would switch from input to output and initially drive low. Again, the I2C module should be used for I2C as it has a special pin driver that is open-drain and also much lower impedence.

In the case of 3.3V/5V interfacing there would be no issue since the I/O pins can be pulled above VDD when they are outputting a high, so when switching to output and the pin comes up high there will be no change in voltage and it can then be pulled low by software.

You are right the behavior (output mode initial state reflects the input logic level) is not exactly what one would expect from open-drain port pins. However, although the port pins don't have an open-drain mode the same functionally can generally be implemented without external components.

-NXP

[lpcware]

Content originally posted in LPCWare by noritan_org on Thu Feb 04 04:55:00 MST 2010
I don't think the input threshold of the standard port pins and PIO0_7 pin is not 1/2 VDD.  LPC111x datasheet Rev.00.13 says VIH(min)=2.0V and VIL(max)=0.8V for all voltage supply conditions in the page 30 and 31.  They are defined as 5.0V tolerant input pins with TTL level threshold.

What I am expecting to an open-drain output port is to have only two kind of states, drive LOW and Hi-Z. I don't expect the port drives HIGH even if the driving period is very short like an glitch.

Please imagine standard I2C type of BUS. Do you expect a device driving the BUS as HIGH strongly ?

[lpcware]

Content originally posted in LPCWare by NXP_USA on Wed Feb 03 20:29:18 MST 2010

---

Quote: noritan_org
I would like to confirm ONE point.

From the behavior explanation, it is concluded that the GPIO port cannot be used as an Open-Drain output, because it may drive HIGH instead of LOW when the DIR bit is set during the signal line is pulled up by a resistor.

---

When switched to output, a pin mirrors the logic state already on it. The threshold should be about 1/2 Vdd. What voltage is your pullup tied to?

[lpcware]

Content originally posted in LPCWare by noritan_org on Wed Feb 03 06:36:53 MST 2010
I would like to confirm ONE point.

From the behavior explanation, it is concluded that the GPIO port cannot be used as an Open-Drain output, because it may drive HIGH instead of LOW when the DIR bit is set during the signal line is pulled up by a resistor.

I know a workaround solution to add an external discrete driver controlled by a GPIO output..  Are there any solution without additional components ?

[lpcware]

Content originally posted in LPCWare by NXP_USA on Tue Feb 02 10:38:26 MST 2010
Hi All,

Here is a description of the I/O port behavior.

The LPC111x and LPC134x parts have a single port data register that provides the following behavior:

Port read: This will always read the pin voltages, input pins output driver state for output pins. The bit masking feature should be used for output writes.

Port write: This will set the value of all of the bits/pins in the port data register, that are configured as outputs. The bit values written to pins set in input mode will not be retained.

Set pin mode to input: The high-current drivers will be disabled. The pin voltage can be controlled by pullups/pulldowns if configured in IOCON.

Set pin mode to output: Upon changing a pin to output mode, it drives the level in the data register. This will be the current logic level on the pin, which could be set by the pullup/pulldown or an external signal.

For example:
-Pin is input, floating high-ish (LPCXpresso LED example when pullup enabled- due to LED forward biasing by pullup, it is probably floating at around 2V)
-Pin mode is set to output
-Pin drives high

-Pin is input/pullup, but pulled down externally for some reason
-Pin mode is set to output
-Pin drives low

The pins mirror the current logic level when they are switched from input to output.

Bit masking: There is an address region for the data register. Writes to this region will set or clear individual bits in the port register. The way this works is low bits in the write address are used to create a mask for the data register write. There is one address bit for each pin (12) in the data register. For an example of this, see the gpio.h file in the LPCXpresso example package.

edited on 1/3/2010- removed RMW language as the port pins do not demonstrate this

-NXP

[lpcware]

Content originally posted in LPCWare by LynnF on Mon Feb 01 05:25:58 MST 2010

---

Quote:
Hello Noritan_org,

We are investigating this behavior and should have more information soon.

-NXP

---

When can we expect a response to your investigation of this issue?

[lpcware]

Content originally posted in LPCWare by NXP_USA on Wed Jan 27 15:28:04 MST 2010

---

Quote: noritan_org
I have confirmed the behavior of the GPIO especially PIO0_7 and found a conclusion.

The initial condition of the GPIO output when DIR is configured as output is depend on the condition of the port during configured as input.

I have tried 4 conditions of MODE bit field of the IOCON_PIO0_7 register.


[LIST]
[*] MODE=00  INACTIVE
[/LIST]
[INDENT] The initial output becomes "0" because the port has an LED and a register which are behave as pull-down.
The initial output becomes "1" when an external 10kohm pull-up resister is attached.
[/INDENT]
[LIST]
[*] MODE=01 PULL-DOWN
[/LIST]
[INDENT] The initial output becomes "0" because the port is pulled down regardless of the LED.
[/INDENT]
[LIST]
[*] MODE=10 PULL-UP (Default)
[/LIST]
[INDENT] The initial output becomes "1" because the internal pull-up is stronger than the external LED and resisters. The potential of the PIO0_7 is 1.767V (56% of 3V3=3.117V) which is between VIH(min)=2.0V and VIL(max)=0.8V of the PIO0_7 port.
[/INDENT]
[LIST]
[*] MODE=11 REPEATER
[/LIST]
[INDENT] The initial output becomes "1" because the condition of the port PIO0_7 is decided as "1" when the MODE is changed from PULL-UP.
[/INDENT]As the results, The reason why the initial condition of the output becomes "1" is THE CHIP ON THE BOARD recognize the potential 1.767V as "1"  The result may be different in other cases.

I found the solution to determine the initial condition of the output is [B][SIZE=3][COLOR=Red]set the MODE bit field as pull-up or pull-down prior to change the DIR bit[/COLOR][/SIZE][/B].

Thank you very much
--
noritan.org  http://noritan.org/  _@"  _@"  _@"

---

Hello Noritan_org,

We are investigating this behavior and should have more information soon.

-NXP

[lpcware]

Content originally posted in LPCWare by noritan_org on Thu Jan 21 21:27:09 MST 2010
I have confirmed the behavior of the GPIO especially PIO0_7 and found a conclusion.

The initial condition of the GPIO output when DIR is configured as output is depend on the condition of the port during configured as input.

I have tried 4 conditions of MODE bit field of the IOCON_PIO0_7 register.


[LIST]
[*] MODE=00  INACTIVE
[/LIST]
[INDENT] The initial output becomes "0" because the port has an LED and a register which are behave as pull-down.
The initial output becomes "1" when an external 10kohm pull-up resister is attached.
[/INDENT]
[LIST]
[*] MODE=01 PULL-DOWN
[/LIST]
[INDENT] The initial output becomes "0" because the port is pulled down regardless of the LED.
[/INDENT]
[LIST]
[*] MODE=10 PULL-UP (Default)
[/LIST]
[INDENT] The initial output becomes "1" because the internal pull-up is stronger than the external LED and resisters. The potential of the PIO0_7 is 1.767V (56% of 3V3=3.117V) which is between VIH(min)=2.0V and VIL(max)=0.8V of the PIO0_7 port.
[/INDENT]
[LIST]
[*] MODE=11 REPEATER
[/LIST]
[INDENT] The initial output becomes "1" because the condition of the port PIO0_7 is decided as "1" when the MODE is changed from PULL-UP.
[/INDENT]As the results, The reason why the initial condition of the output becomes "1" is THE CHIP ON THE BOARD recognize the potential 1.767V as "1"  The result may be different in other cases.

I found the solution to determine the initial condition of the output is [B][SIZE=3][COLOR=Red]set the MODE bit field as pull-up or pull-down prior to change the DIR bit[/COLOR][/SIZE][/B].

Thank you very much
--
noritan.org  http://noritan.org/  _@"  _@"  _@"

[lpcware]

Content originally posted in LPCWare by igorsk on Thu Jan 21 15:44:08 MST 2010
Check the pull-up configuration. From UM10375 chapter 5, section 3.2:
"The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. [B]The default value is pull-up enabled[/B]."