Interrupt latency

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Interrupt latency

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by rodinger on Sun Jan 02 11:49:06 MST 2011
Hello. I am writing some time sensitive assembly code on the LPC-LINK/LPC1114 and I have measured the time to enter the interrupt service routine to be about 30 cycles. I didn't expect it to be this long. From reading various datasheets on the web, it sounded like the interrupt latency should be fixed at 16 cycles. Is the interrupt latency really about 30 cycles or is there something wrong with my software or hardware? Thank you.

Method
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To measure it, I am using the 32-bit timer 0. I have set it up to do PWM and have enabled the interrupt on match. In the interrupt routine, I pulse an IO pin (see appendix). Then with the scope, I measure the time from when the match occurs and the PWM goes high to the time that I see the pulse on the IO pin. I timed this at 39 cycles. Then I subtract a few cycles needed to actually pulse the pin. That's how I come up with the 30 cycles. The core is running at 48Mhz. I have confirmed this with a couple of different ways so I am quite sure that the core is running at the speed I think it is.

Appendix
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Here is the interrupt code that I use to pulse an IO pin

TIMER32_0_IRQHandler:
ldr r0, LED_data         // get the register address for the IO pin
ldr r1, LED_data + 4  // get the value to make it go high
ldr r2, LED_data + 8  // get the value to make it go low

str r1, [r0]   // IO pin goes high
str r2, [r0]   // IO pin goes low
...
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by  on Wed Jan 05 20:36:23 MST 2011
I think it is reasonable, 22 cycles are needed for M0 to detect INT and go to the beginning of the ISR. And there are 4 instructions before IO toggling operation, each one need 2 cycles for M0 fetch code from flash (only 1 cycle from RAM, so maybe less latency is needed for ISR located at RAM).
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