Content originally posted in LPCWare by NXP_Europe on Tue May 08 16:41:20 MST 2012
Hello Luis,
POR comes in at 'very' low Vdd and is not activated by an external reset, when the Vdd stays at e.g. 3V3.
BOD becomes active after building up the 3V3. When the Vdd drops, the BOD interrupt and BOD reset will become active under the programmed levels.
Zero is right, that you should add a pull up of appr. 10k ... 12k
You allready mounted the capacitor. This capacitor is used to keep the reset low for a short time, just after power up.
Let us know whether the problem (indefined state) is solved.