;-----------------------------------------------------------------------!
; Setup the Interrupt System!
;-----------------------------------------------------------------------!
fn InitNVIC
;---------------------------------------;
movsr3, sramBase; vector table
movsr0, 0;
strr0, [r3], 4; stack <used for tick count>
strr0, [r3], 4; reset <used for day roll over >
ldrr1, =NMI;
strr1, [r3], 4; NMI
ldrr1, =HardFault;
strr1, [r3], 4; Hard Fault
ldrr1, =MMFault;
strr1, [r3], 4; Memory Management Fault
ldrr1, =BusFault;
strr1, [r3], 4; Bus Fault
ldrr1, =UsageFault;
strr1, [r3], 4; Usage Fault
strr0, [r3], 4; unused
strr0, [r3], 4; unused
strr0, [r3], 4; unused
strr0, [r3], 4; unused
ldrr1, =Missing;
strr1, [r3], 4; SVC
strr1, [r3], 4; Debug Monitor
strr0, [r3], 4; unused
strr1, [r3], 4; Pending SVC
ldrr2, =SysTick;
strr2, [r3], 4; SysTick
movsr2, nIrq; now all the peripheral IRQs
0:strr1, [r3], 4;
subsr2, 1;
bne0b;
;---------------------------------------;
movsr3, sysBase; Cortex system control block
mvnsr1, r0;
strr1, [r3, irqClrEnable]; disable all irq
strr1, [r3, irqClrEnable2];
strr1, [r3, irqClrPending]; clear all pending
strr1, [r3, irqClrPending2];
movsr1, (0<<8); set sub-priority bits (1)
movtr1, 0x05FA; access key
strr1, [r3, sysReset];
movsr1, (1<<9)+(0<<4)+(1<<3); StackAlign/!DivZero/UnalignTrap
strr1, [r3, sysConfig];
addsr0, r3, irqPriority; reset all priorities to lowest
movsr2, nIrq;
movsr1, (31<<3);
0:strbr1, [r0], 1;
subsr2, 1;
bne0b;
strbr1, [r3, sysPriSysTick]; including the sys tick handler
movsr1, (0<<3); highest 3 priorities for faults
strbr1, [r3, sysPriBF]; bus fault
movsr1, (1<<3);
strbr1, [r3, sysPriMM]; mm fault
movsr1, (2<<3);
strbr1, [r3, sysPriUF]; usage fault
;---------------------------------------;
movsr1, sramBase; relocate the vector table
strr1, [r3, sysVTab];
movsr1, (1<<18)+(1<<17)+(1<<16); enable the fault handlers
strr1, [r3, sysFaultEnable];
bxlr; return
fe InitNVIC
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