Content originally posted in LPCWare by Jesse.Rosenberg on Wed Sep 22 12:35:01 MST 2010
The clock output pin is primarily intended for diagnostic purposes, rather than for clock synthesis. Using a divider value of 2, for instance, can be used to observe an internal 100MHz clock frequency using lower end lab equipment, such as a USB based oscilloscope with limited bandwidth.
You should bear in mind that should your design make use of in system programming (ISP) via the chip's boot loader for software updates, you'll most likely be using P0_1, which is typically a clock output pin.