(GPIO) structure definitions

[lpcware]

Content originally posted in LPCWare by wortel on Tue Dec 21 06:24:14 MST 2010
Maybe a very stupid question, but were can i find explanations about the CMSIS structure definitions?

If I see the LPC_GPIO3 structure I see various options (MASKED_ACCESS is used in the library to set/clear an IO)
I want to toggle a pin the fastest way, with the library I already managed it.

This same hold for other peripherals were I cannot find the documentation about it (e.g. I2C).

Original Attachment has been moved to: 1100920_ADCvhd.txt.zip

[lpcware]

Content originally posted in LPCWare by wortel on Tue Dec 21 07:49:24 MST 2010
Ah, accedently downloaded the datasheet instead of the manual.

Great help, many thanks!

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Tue Dec 21 07:42:10 MST 2010
Hello wortel,

make for yourself a small list with links. All these links are pointing to documents, e.g. User Manual UM10375 (= LPC13xx).

By simply using the [B]"find function"[/B] lots of info can be found very simple.

e.g. What is IEV?

(see chapter 8)
IEV: [FONT=Arial][SIZE=1][FONT=Arial][SIZE=1][SIZE=2]Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11).[/SIZE][/SIZE][/FONT][SIZE=1]

[/SIZE][/SIZE][/FONT]

[lpcware]

Content originally posted in LPCWare by CodeRedSupport on Tue Dec 21 06:56:55 MST 2010
Details of the GPIO registers can be found in "Chapter 8: LPC13xx General Purpose I/O (GPIO)" of LPC13xx User Manual - link given in my previous post.

[lpcware]

Content originally posted in LPCWare by wortel on Tue Dec 21 06:49:14 MST 2010
Wow, great! What a fast response.

I already examined the first link before but I could find it.
I`m using indeed the LPC13 series.

I`m refering to e.g. this structure;

For example, what do IS/IBE/IEV etc. mean? Where do I've to look for this?
I`m coming from AVR and PIC controllers, there I usually download their specific datasheet and all of the registers are inside (and explained).
I don't know how I have to do it with the NXP ARM.

/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
  union {
    __IO uint32_t MASKED_ACCESS[4096];
    struct {
         uint32_t RESERVED0[4095];
    __IO uint32_t DATA;
    };
  };
       uint32_t RESERVED1[4096];
  __IO uint32_t DIR;
  __IO uint32_t IS;
  __IO uint32_t IBE;
  __IO uint32_t IEV;
  __IO uint32_t IE;
  __IO uint32_t RIS;
  __IO uint32_t MIS;
  __IO uint32_t IC;
} LPC_GPIO_TypeDef;

[lpcware]

Content originally posted in LPCWare by CodeRedSupport on Tue Dec 21 06:35:43 MST 2010
General information on CMSIS in LPCXpresso can be found in the following FAQ:

http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS

However, the CMSIS headers basically just implement pointers onto the peripheral registers inside the MCU. Thus it sounds like what you really want to be looking at is the user manual for the part that you are using, which, as you mention masked accesses, I would imagine is LPC11 or LPC13:

http://ics.nxp.com/products/lpc1000/lpc1100/lpc11xx/~LPC1114/#LPC1114
http://ics.nxp.com/products/lpc1000/lpc13xx/~LPC1343/#LPC1343

Regards,
CodeRedSupport