Content originally posted in LPCWare by NXP_USA on Fri Jul 15 16:10:11 MST 2011
On the Cortex-M3: Most instructions are a single clock cycle except for branches, which are two clock cycles.
On the Cortex-M0: Most instructions are a single clock cycle unless they fetch data. When an instruction fetches data from memory (not immediate or register values), it takes two clock cycles (because the M0 core only has one bus). Branches are 3 clock cycles.
-NXP