Cortex-M3 Pipeline Stalls

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sat Aug 09 07:58:10 MST 2014
NOTE: refering the the Cortex-M3 specifically.

Where can I find information about whether LDR instructions cause a stall if the destination register is used in the immediately following instruction -- if indeed this ever occurs. [And other causes of a pipeline stall.]

The exellect book "ARM a system developer's guide" disccuses this issue for ARM9,10,11 cores but
has no information about the Cortex-M3.

I tried reading the Arm Architecture v7M and the Cortex-M3 TRM but didn't get anywhere.

Regards, Mike

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Mon Aug 11 04:45:53 MST 2014
Thank you for the pointer -- Mike

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Mon Aug 11 00:28:06 MST 2014
The pipelines on Cortex-M parts is fairly simple, certainly compared to things like ARM11 (and later A class parts). The main information I can recall seeing on this area is at:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337i/CHDIJAFG.html

Regards,
LPCXpresso Support