Automatic splitting of section.

[lpcware]

Content originally posted in LPCWare by coco on Mon Feb 10 01:56:07 MST 2014
Hi,

Currently I'm using LPC1830 and it has 5 non-contiguous RAM region. Is there any linker that supports automatic splitting of a section (i.e. text) into multiple region? For example something like this:  http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=spraa46a&fileType=pdf (page 5). I'm currently using GCC 4.6, but I'm open to any suggestion (i.e. Keil, IAR, or others) if they support this feature.

Thanks.

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Wed Feb 19 15:52:08 MST 2014
As previously stated, there is currently no way of "automatically flood filling" multiple RAM regions like this in LPCXpresso - though this is an area for have earmarked for looking into at some point in the future.

If you are running out of space in the default first RAM bank, then the simplest thing to do is leave most of your data in the default first RAM bank, use the macros described in the FAQ given in our previous post to move specific large array or variables into another RAM bank, and also move the stack and heap into another RAM bank too.

Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by vostro1000 on Wed Feb 19 12:15:05 MST 2014
I also have this same question... How to distribute .bss .data sections automatically by the segmented ram regions in lpcxpresso? I know that lpcxpresso  use the first region to place stack and heap but how to use the other sections automatically when the first section are full?

[lpcware]

Content originally posted in LPCWare by coco on Wed Feb 12 19:14:21 MST 2014
I'm using LPC1830 , so this is a sample of the memory configuration:

  RamLoc96 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x18000 /* ram1 = 96k */
  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* ram2 = 40k */
  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* ram3 = 32k */
  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* ram4 = 16k */
  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* ram5 = 16k */
  RO_MEM (rx) : ORIGIN = 0x14000000, LENGTH = 0x200000 /* 2MB */

So I would like to place all my .bss and .data either to ram1 / ram2 / ram3 / ram 4 / ram5.
Notice that the RO_MEM (external flash) address is in between ram2 and ram3, so I can't declare a dummy variable to be placed in that address.

[lpcware]

Content originally posted in LPCWare by wmues on Tue Feb 11 04:22:42 MST 2014
You may want to create ONE continuous RAM region in your linker script, containing all available RAM. Then you may place some dummy variables at fixed locations, so that the linker does not place your variables in non-existing RAM.

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Tue Feb 11 03:35:59 MST 2014
There is no automated way of doing what I think you are asking for in LPCXpresso, but you can quite easily use specific RAM blocks for specific data items…

http://www.lpcware.com/content/faq/lpcxpresso/data-different-ram-blocks

If you can explain in more detail exactly what you are trying to achieve, we might be able to provide further advice.

Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by coco on Mon Feb 10 18:55:52 MST 2014
I agree that there are some performance sensitive code that will require manual management, but for majority of the code/data it probably doesn't make a lot of difference. Especially in my use case, majority of the code is running in the external flash, and the RAM will be mainly use for .data/.bss. Also we are talking about hundreds/thousand of source files involved , it seems to be very useful to have them automatically split into multiple region. I'm considering to write a  script that parse the object file section and fit them optimally to different RAM region. But this problem seems to be too common so I'm just wondering whether there are ready solution out there.

[lpcware]

Content originally posted in LPCWare by rocketdawg on Mon Feb 10 14:22:51 MST 2014
You really want to manage the memory yourself with the linker scripts.

To optimize the CPU performance the ARM Cortex-M3 has three buses for Instruction (code) (I) access, Data (D) access, and System (S) access. The I- and D-bus access memory space is located below 0x2000 0000, the S-bus accesses the memory space starting from 0x2000 0000. When instructions and data are kept in separate memories, then code and data accesses can be done in parallel in one cycle. When code and data are kept in the same memory, then instructions that load or store data may take two cycles.