ADC clock speed.

[lpcware]

Content originally posted in LPCWare by micrio on Mon Aug 27 09:37:17 MST 2012
While doing some ADC code I noticed that the CLKDIV seems to be wrong.
This is for a LPC1114 running at 48 MHz on the internal oscillator.

LPC_ADC->CR = ((SystemCoreClock/LPC_SYSCON->SYSAHBCLKDIV)/ADC_CLK - 1) << 8;

[SIZE=2]I copied this code from the examples.[/SIZE]
[SIZE=2]This piece of code sets CLKDIV to a value of 9.   The actual divisor ends up being 10  (9 + 1).   [/SIZE]
[SIZE=2]Since [/SIZE][SIZE=2]the system is running at 48 MHz the ADC clock will be 4.8 MHz which exceeds[/SIZE]
[SIZE=2]the spec of 4.5 MHz.   Is this correct?   Should the CLKDIV actually be 10?[/SIZE]

[SIZE=2]Thanks,[/SIZE]
[SIZE=2]Pete.[/SIZE]

[lpcware]

Content originally posted in LPCWare by NXP_Europe on Wed Aug 29 14:13:46 MST 2012
Hello micrio,

I think you are right. The value of 4.8MHz is a little out of spec.

In User Manual UM10398:

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Quote:

[SIZE=1][FONT=Arial][SIZE=1][FONT=Arial][B][FONT=Arial][SIZE=1][COLOR=#005042][FONT=Arial][SIZE=1][COLOR=#005042][FONT=Arial][SIZE=1][COLOR=#005042]Table 363. A/D Control Register (AD0CR - address 0x4001 C000) bit description[/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][/B]
[LEFT][/FONT][/SIZE][/FONT][/SIZE][SIZE=1][FONT=Arial][SIZE=1][FONT=Arial]15:8 CLKDIV [/FONT][/SIZE][/FONT][/SIZE]
[SIZE=1][FONT=Arial][SIZE=1][FONT=Arial]The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which[/FONT][/SIZE][/FONT][/SIZE]
[SIZE=1][FONT=Arial][SIZE=1][FONT=Arial]should be less than or equal to 4.5 MHz. Typically, software should program the smallest[/FONT][/SIZE][/FONT][/SIZE]
[SIZE=1][FONT=Arial][SIZE=1][FONT=Arial]value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such[/FONT][/SIZE][/FONT][/SIZE][SIZE=1][FONT=Arial]
[SIZE=1][FONT=Arial]as a high-impedance analog source) a slower clock may be desirable.[/FONT][/SIZE][/LEFT]
[/FONT][/SIZE]

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Noticed well! We will correct that.